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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TEMUX 84
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PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 8: JANUARY 2003
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PMC-Sierra, Inc.
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DATA SHEET
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MULTIPLEXER
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105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
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PM8316
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Disclaimer
Trademarks
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PMC-Sierra, Inc.
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The technology discussed is protected by one or more of the following Patents: U.S. Patent No. 5,640,398 Canadian patent 2,161,921 Relevant patent applications and other patents may also exist.
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Patents
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TEMUX, SBI, and PMC-Sierra are trademarks of PMC-Sierra, Inc.
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In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.
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None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.
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105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
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PMC-1991437 (R8), ref PMC-1991191 (P9)
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The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers' internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc.
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(c) 2003 PMC-Sierra, Inc.
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Copyright
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Legal Information
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
1 2 3 4 5
Oct 27, 1999 Jan 24, 2000 Oct 19, 2000 May 4, 2001 Oct 22, 2001
Original Document. Advance version. Upgrade document from Preview to Advance
Preliminary version released in conjunction with Rev. A tapeout Datasheet updated to reflect Issue 5 of PMC-1991191.
see the marked corrections in the text.
Change to Section 1: HDLC interface with 127 bytes of buffering for terminating the facility
buses.
and either the ingress or egress T1 or E1 signals are routed to the T1 or E1 framers monitoring and HDLC termination.
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The Ingress Flexible Bandwidth Enables (IFBWEN[3:1])... The IFBWEN[3:1] inputs are constrained such that the maximum data rate of each of IFBWDAT[3:1] is less than 48.96 Mbit/s.
System Reference Clock (SREFCLK)... This clock must be phase locked to LREFCLK and can be external connected to LREFCLK. When passing transparent virtual tributaries between the telecom bus and the SBI bus, SREFCLK must be the same frequency as LREFCLK (i.e. S77 = L77). Change in second note to pin table: The outputs TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1], RGAPCLK/RSCLK[3:1], RDATO[3:1], RFPO/RMFPO[3:1], ROVRHD[3:1], TFPO/TMFPO/TGAPCLK[3:1], SBIACT, LAOE/LATPL, RECVCLK1, RECVCLK2, RECVCLK3, CASID[21:1], CCSID, TS0ID, TDO and INTB have 4 mA drive capability... The bidirectional SBI signal SDC1FP has 8mA drive capability. MVID[21:1] have 8mA drive capability. Changes to section 9.1 New: Section 9.2 Change to Section 9.3: For ESF, out-of-frame declaration is based strictly on Frame Alignment Signal (F1-F6) bit errors; a new frame search is never initiated upon
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SONET/SDH (i.e. LINEOPT_SPEx = 01), RSCLK is a gapped version of CLK52M.
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Framer Recovered Clock (RSCLK[3:1])... When a DS3 is demapped from
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Changes in pin table:
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for performance monitoring purposes, which include error event accumulation, alarm
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Change to Section 6: In this configuration the T1 and E1 transmit framers are disabled
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New: Figure 2 TEMUX 84 Block Diagram
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New: Figure 1 Fractional DS3 Application
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Change to Section 1: Seamlessly interfaces with 77.76 MHz Drop and 77.76 MHz Add
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data link.
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Datasheet updated to reflect Issue 6 of PMC-1991191. Go to the sections noted below to
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Issue No.
Issue Date
Details of Change
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REVISION HISTORY
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Change to Section 9.6: Received data is placed into a 127-byte FIFO buffer.
Changes to Section 9.21: Add E3 New: Table 1 Path Signal Label Mismatch State New: Section 19.37.1
with any other pins. The CCSID[1:3] outputs is always available provided
Changes to Table 2 Register Memory Map:
0,1,2...) SREFCLK cycles before the LAC1 pulse.
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New: Table 3 TVT Constraints for 77.76MHz Change to Section 12.2.3: TVTs are not supported for this bus configuration. Change to Section 12.3.2: The T1 framer will determine frame alignment within 13ms Change to Step 10 in 12.8: If PBS[2:0] = 1XX, discard the data byte read in step 5, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet. Changes to Section 12.14 and Fig 27: Add E3 Change to text just before Table 32: The signaling contained within the robbed bit positions of the DS0s will also have an arbitrary alignment relative to the P1P0 bits. Change to text just after Table 38: When carrying framed E3, only the ITU-T Rec. G.751 format is supported. Unframed E3 is carried clear channel. Changes to Table 39 E3 Frame Stuffing Format Just before Figure 61: The LAC1J1V1 signal is high when the LAPL signal is high to mark every J1 byte of each of the three STS-1 SPEs. The LAV5 signal pulses high to mark the V5 bytes of each tributary. LATPL, multiplexed with LAOE shown separately in [x-
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Change to Section 12.2.2: When TVTs are supported an additional constraint exists between SAC1FP and LAC1. Table 16 gives the permissible combinations.
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Change to bullet in Section 12.2.1: The SAC1FP pulse must be 3n +/ 1 (where n =
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0x40*N
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RTTB TU3 or TU #1 in TUG2 #1 to TUG2 #7, TIM Interrupt
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0x01EA
INSBI E1 Thresholds Register
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INSBI T1 Thresholds Register
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0x0157
SIGX Configuration
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Change to Section 9.44: The TEMUX 84 identification code is 183160CD hexadecimal.
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New: Section 9.43.1 Burst Lengths on Ingress Flexible Bandwidth Port
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Change to Section 9.43: SPE (48.96 Mbit/s).
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CMV8MCLK, CMVFPB and CMVFPC are active.
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Change to end of Section 9.40 The CCS H-MVIP interface, CCSID[1:3], is not multiplexed
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Changes to Section 9.14
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excessive CRC-6 errors.
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
registers. A pointer of 522 decimal is illustrated in [x-ref]. Changes to Table 51 Changes to Table 54 Changes to Table 56 Changes to Table 58 Changes to Table 62 6 Apr `02 Change bars relative to Issue 5.
[Errata Item] The SBI Alarms description now describes the necessary conditions for
bytes. The description of the 77MHz telecom add bus makes it clear that LATOHEN signal.
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simultaneously with SPEs over the telecom bus interface. Text added to Functional Description section explaining what can/ cannot be done dependent on config bits.
[Errata Item] In order for the TEMUX 84 to work along with TBS/TSE and Spectra devices in an ADM the TEMUX 84 must place a constant value in the H1/H2 fields that equals a valid pointer corresponding to the chosen, fixed SPE offset. Added text to the VTPP portion of the functional description. All references to receive alarms affecting bit 4 of V5 removed. This behaviour is appropriate according to G.707-2000. [Errata Item] The DS3 mapper/demapper in TEMUX 84 operates in AU3 mode only. Note added that a mix of T1/E1s mapped into SDH AU4 SPEs with DS3 Mapper/Demapper SPEs is not allowed. The "Egress H-MVIP System Interface" section now includes text about avoiding controlled frame slips. [Errata Item] For each reference to the DS3 linkrate, a comment has been added explaining that the ClkRate[1:0] information is not valid when the DS3 has been demapped from SONET/SDH by the D3MD function. LAOE/LATPL has the same pad as all other Combus Add outputs, and an 8mA drive. Functional timing diagrams for the Ingress and Egress Flexible Bandwidth ports now
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More information about whether the TEMUX 84 supports DS3 LIU interfaces
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Some A.C. parameters were added to TICLK and RCLK.
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must be set on all 4 devices so that the combined telecom bus will have a valid LAPL
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payload bytes as configured in the TTMP, and optionally in the J1, V1, and overhead
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The pin description for LAPL now clearly indicates that it will be driven only for
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LADDOE register bit settings. Also, the 77.76MHz tPtel parameter has been changed.
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[Errata Item] In the Functional Timing section there is a new description of the
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setting the ALM bit for T1, E1, DS3 and E3.
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have an alignment determined by the SONET/SDH Transmit Pointer Configuration
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location LATPL low indicates a positive pointer justification. The three STS-1 SPEs
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indicates a negative pointer justification when high and during the byte after the V3
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ref], indicates valid tributary payload when high. During the V3 location LATPL
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
In the "T1 Bit Oriented Code Generation" section, more explanation about what happens if the code is overwritten before transmission is finished.
In the "H-MVIP Data Format" section, some text has been added describing what

The description for MFSDC1FP has been changed.
=4*(MVED index - 7*(SPE-1) - 1) + DS1 =4*(MVED index - 7*(SPE-1) - 1) + E1
There is a new section outlining the PRGD blocks, mentioning how to program TAP &

Changed Vt- from 0.8V to 0.6V for Schmitt trigger pads. Noted that L77 and S77_MVED_3 (S77 and MVED[3] pin D10) are Schmitt trigger inputs.
Some minor changes to "Notes on Pin Desciptions" Item #2, Output drive
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Section 15: DC Characteristics, VOH VOL, minor corrections: 1) CASID[7:0] changed to CASID[21:1] 2) MVID[7:0] changed to MVID[21:1]
Documented Line Side SBI operation throughout the document including the block diagram Added 3 more block diagrams showing Transmux mode, Mapper/Mux mode and the placement of the T1/E1 framer and transmitter in High Density Framer mode. Updated the RCLK pin description to limit the tolerance on the input clock to maintain a DS1 demultiplexed clock within the standard's requirements. Updated the RGAPCLK/RSCLK pin description to note that an external jitter attenuator is required when connected the output clock to the PM73122 AAL1gator32 device. Updated the TFPI/TMFPI pin description to correct the location of the TDATIFALL bit. Updated the LAOE/LATPL pin description changing its output type to a tristate output. Updated the CLK52M pin description stating that when demapping a DS3 from SONET its frequency must be 44.928 MHz.
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capabilities.
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Changed tSsbiadd @ 77MHz to 2.7ns from 3ns.
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April 2002
Updated table in Operation section (Table 16: TVT Constraints for 77.76MHz)
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LENGTH registers to generate specific PRBS patterns and Repetitive patterns.
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Changes to the formula for calculating the SBI index value:
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[Errata Item] New comments in "Clock and Frame Synchronization Constraints".
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Flexible bandwidth now spec'd for a load of 50pf on all outputs.
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happens in applications where the F-bit value is not overwritten by the transmitter.
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Updated the SREFCLK pin description adding that it can tolerate a +/-50 ppm
SBI and H-MVIP buses are both not being used.
Updated the MVID[21:1] output pins' current drive strength to 4 mA. Updated section 9.2 Transmultiplexing to state that section 12.2.3 of the datasheet

Updated an input to a multiplexer in Figure 17 DS3/E3 Configuration Options. Updated a register bit setting in section 9.20 Receive Tributary Byte Synchronous Demapper and section 9.25 Transmit Tributary Byte Synchronous Mapper.
through an external jitter attenuator before connecting it to the PM73122 AAL1gator32 device. Also removed the 51.84 MHz option for CLK52M.
Configuration (SBI Bus), 0x01C6 DLL Delay Tap Status (SBI Bus), 0x01C7 DLL Delay Tap Status (TelecomBus) and 0x073F DLL Control Status (TelecomBus).
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Updated the Version Number and Device Identification values of Table 11 Identification Register in section 11.1 JTAG Test Port.
Updated the Id bit for OEB_RECVCLK_1 in Table 12 Boundary Scan Register of 11.1 JTAG Test Port. Updated section 12.2.2 SBI and Telecom Buses Both 19.44 MHz with TVT constraints when the IVTPP or EVTPP are bypassed. Updated section 12.2.3 SBI and Telecom Buses Both 77.76 MHz stating that the constraints must be followed for transmux mode. Updated section 12.3 SLC96, removing all references to using the H-MVIP bus. Updated section 12.10 Using the Internal T1/E1 Data Link Transmitter noting that the minimum packet size for THDL is 2 bytes. Updated section 12.14 DS3 and E3 Loopback Modes removing the sentence that states a DS3 AIS can be transmitted when a DS3 digital diagnostic loopback is enabled. Added section 12.20 Configuring the Line Side SBI. Updated the Lead Temperature Maximum rating to 225C from 230C in Table 47
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Control Status (SBI Bus), 0x073C DLL Configuration (TelecomBus), 0x073E DLL
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Added the following registers to Table 9 Register Memory Map: 0x01C4 DLL
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Updated 9.21.3 DS3 Desynchronizer to note that the demapped clock must pass
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National Use, Sa, bits.
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Updated section 9.11, E1 Transmitter, with details on the operation of inserting
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followed to operate correctly.
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sequence of the TEMUX 84 Programmer's Guide for transmux mode must be
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must be followed when operating in transmux mode. Also that the initialization
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Updated the SDC1FP pin description noting that the input must be held low when the
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accurate clock source when operating in serial DS3 mode.
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Corrected the maximum RCLK[3:1] frequency for E3 mode in Table 53: DS3/E3 Receive Interface Timing.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Absolute Maximum Ratings.
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
5
BLOCK DIAGRAM ..................................................................................26
5.2 5.3 5.4 5.5 6 7 8 9
M13 MULTIPLEXER MODE BLOCK DIAGRAM ..........................27
PIN DESCRIPTION ................................................................................39
9.1
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9.2 9.3 9.4 9.5 9.6
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FUNCTIONAL DESCRIPTION................................................................81 TRANSPARENT VIRTUAL TRIBUTARIES...................................81 TRANSMULTIPLEXING ...............................................................82 T1 FRAMING ...............................................................................83 E1 FRAMING ...............................................................................85 T1/E1 PERFORMANCE MONITORING.......................................93 T1/E1 HDLC RECEIVER .............................................................93
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PIN DIAGRAM ........................................................................................38
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DESCRIPTION .......................................................................................33
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T1/E1 FDL EXTRACTION/INSERTION AND ALARM/ERROR RESPONSE .................................................................................29
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DS3/E3 FRAMER ONLY BLOCK DIAGRAM ...............................29
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VT/TU MAPPER ONLY MODE BLOCK DIAGRAM......................28
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TOP LEVEL BLOCK DIAGRAM ...................................................26
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APPLICATION EXAMPLES ....................................................................22
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REFERENCES .......................................................................................18
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APPLICATIONS ......................................................................................17
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FEATURES...............................................................................................1
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LEGAL INFORMATION .......................................................................................2
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CONTENTS
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22
T1/E1 RECEIVE PER-CHANNEL CONTROL..............................95
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9.23 9.24 9.25 9.26
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RECEIVE TRIBUTARY BYTE SYNCHRONOUS DEMAPPER ..131 DS3 MAPPER DROP SIDE (D3MD) ..........................................132 TRANSMIT TRIBUTARY PATH OVERHEAD PROCESSOR (TTOP)135
TRANSMIT REMOTE ALARM PROCESSOR (TRAP)...............136 TRANSMIT TRIBUTARY BIT ASYNCHRONOUS MAPPER (TTMP)137 TRANSMIT TRIBUTARY BYTE SYNCHRONOUS MAPPER ....138 DS3 MAPPER ADD SIDE (D3MA) .............................................139
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RECEIVE TRIBUTARY BIT ASYNCHRONOUS DEMAPPER (RTDM) ......................................................................................129
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RECEIVE TRIBUTARY TRACE BUFFER (RTTB)......................128
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RECEIVE TRIBUTARY PATH OVERHEAD PROCESSOR (RTOP) ...................................................................................................125
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TRIBUTARY PAYLOAD PROCESSOR (VTPP) .........................123
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DS3/E3 FRAMING, PERFORMANCE MONITORING AND MULTIPLEXING .........................................................................106
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T1/E1 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION (PRBS).........................................................105
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T1/E1 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATORS ...........................................................................99
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T1/E1 HDLC TRANSMITTERS ....................................................98
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E1 TRANSMITTER ......................................................................97
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T1 TRANSMITTER ......................................................................96
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T1/E1 SIGNALING EXTRACTION ...............................................95
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T1/E1 ELASTIC STORE (ELST) ..................................................94
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
9.29 9.30 9.31 9.32 9.33 10 11
INSERT SCALEABLE BANDWIDTH INTERCONNECT (INSBI)145 FLEXIBLE BANDWIDTH PORTS ..............................................146
NORMAL MODE REGISTER DESCRIPTION ......................................175
12.6 12.7
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12.10 USING THE INTERNAL T1/E1 DATA LINK TRANSMITTER......210 12.11 USING THE TIME-SLICED T1/E1 TRANSCEIVERS.................212
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12.5
SERVICING INTERRUPTS........................................................195 USING THE PERFORMANCE MONITORING FEATURES .......196 USING THE INTERNAL DS3 OR E3 HDLC TRANSMITTER ....200 USING THE INTERNAL DS3 OR E3 DATA LINK RECEIVER ...204 USING THE INTERNAL T1/E1 DATA LINK RECEIVER.............208
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DS3 FRAME FORMAT...............................................................193
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12.3
SLC96 .....................................................................................191
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12.2
CLOCK AND FRAME SYNCHRONIZATION CONSTRAINTS ...188
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12.1
TRIBUTARY INDEXING.............................................................186
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OPERATION .........................................................................................186
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11.1
JTAG TEST PORT .....................................................................179
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TEST FEATURES DESCRIPTION .......................................................176
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MICROPROCESSOR INTERFACE ...........................................148
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JTAG TEST ACCESS PORT......................................................147
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EXTRACT SCALEABLE BANDWIDTH INTERCONNECT (EXSBI) ...................................................................................................144
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INGRESS SYSTEM H-MVIP INTERFACE.................................142
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EGRESS H-MVIP SYSTEM INTERFACE ..................................141
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
12.14 DS3 AND E3 LOOPBACK MODES............................................217
12.19 JTAG SUPPORT ........................................................................252
13.8
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13.10 EGRESS FLEXIBLE BANDWIDTH TIMING ..............................285 13.11 INGRESS FLEXIBLE BANDWIDTH TIMING .............................286 ABSOLUTE MAXIMUM RATINGS........................................................288 D.C. CHARACTERISTICS....................................................................289
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13.6
SBI DROP BUS INTERFACE TIMING .......................................281 SBI ADD BUS INTERFACE TIMING ..........................................282 EGRESS H-MVIP LINK TIMING ................................................284 INGRESS H-MVIP LINK TIMING ...............................................284
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SONET/SDH SERIAL ALARM PORT TIMING ...........................280
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13.4
TELECOM ADD BUS INTERFACE TIMING...............................276
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13.3
TELECOM DROP BUS INTERFACE TIMING............................272
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13.2
DS3 AND E3 SYSTEM SIDE INTERFACE TIMING...................268
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13.1
DS3 LINE SIDE INTERFACE TIMING .......................................264
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FUNCTIONAL TIMING..........................................................................264
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12.20 CONFIGURING THE LINE SIDE SBI ........................................260
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12.18 DS3 AND FULL FEATURED T1/E1 PATTERN GENERATION AND DETECTION ..............................................................................248
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12.17 H-MVIP DATA FORMAT .............................................................243
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12.16 SBI BUS DATA FORMATS .........................................................221
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12.15 TELECOM BUS MAPPER/DEMAPPER LOOPBACK MODES..220
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12.13 T1/E1 FRAMER LOOPBACK MODES.......................................215
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12.12 T1 AUTOMATIC PERFORMANCE REPORT FORMAT .............213
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
18 19
ORDERING AND THERMAL INFORMATION ......................................320
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MECHANICAL INFORMATION.............................................................321
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TEMUX 84 TIMING CHARACTERISTICS ............................................296
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MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......292
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
xi
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
FIGURE 6 FIGURE 7 FIGURE 8 FIGURE 9
- VT/TU MAPPER BLOCK DIAGRAM..........................................28
- HIGH DENSITY FRAMER MODE T1/E1 BLOCK DIAGRAM ....30
FIGURE 13 - JITTER TOLERANCE T1 MODES...........................................101
FIGURE 16 - JITTER TRANSFER E1 MODES .............................................104
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
FIGURE 19 - INGRESS CLOCK SLAVE - H-MVIP .......................................143 FIGURE 20 - INSERT SBI .............................................................................146 FIGURE 21 - DS3 FRAME STRUCTURE .....................................................193
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FIGURE 18 - EGRESS CLOCK SLAVE - H-MVIP.........................................141
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FIGURE 17 - DS/E3 CONFIGURATION OPTIONS.......................................107
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FIGURE 15 - JITTER TRANSFER T1 MODES .............................................103
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FIGURE 14 - JITTER TOLERANCE E1 MODES...........................................102
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FIGURE 12 - CRC MULTIFRAME ALIGNMENT ALGORITHM .......................89
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FIGURE 11
- PIN DIAGRAM...........................................................................38
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FIGURE 10 - TRANSMUX MODE T1/E1 BLOCK DIAGRAM ..........................32
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- MAPPER/MULTIPLEXER MODE T1/E1 BLOCK DIAGRAM .....31
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- DS3/E3 FRAMER ONLY MODE BLOCK DIAGRAM..................29
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FIGURE 5
- M13 MULTIPLEXER BLOCK DIAGRAM....................................27
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FIGURE 4
- TEMUX 84 BLOCK DIAGRAM...................................................26
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FIGURE 3
- FRACTIONAL DS3 APPLICATION ............................................24
20
04
FIGURE 2
- HIGH DENSITY FRAME RELAY APPLICATION .......................23
07
FIGURE 1
- ANY-SERVICE-ANY-PORT APPLICATION................................22
:4
3:
LIST OF FIGURES
25
xii
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
FIGURE 24 - FER COUNT VS. BER (T1 ESF MODE)..................................198
FIGURE 32 - DS3 AND E3 LINE LOOPBACK DIAGRAM .............................219
FIGURE 34 - TELECOM DIAGNOSTIC LOOPBACK DIAGRAM ..................220
FIGURE 37 - BOUNDARY SCAN ARCHITECTURE .....................................252
FIGURE 39 - INPUT OBSERVATION CELL (IN_CELL) ................................257
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
FIGURE 42 - LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 259
FIGURE 43 -PIN CONNECTION DIAGRAM FOR LINE SIDE SBI................261 FIGURE 44 - RECEIVE BIPOLAR DS3 STREAM.........................................264
xiii
Co
FIGURE 41 - BIDIRECTIONAL CELL (IO_CELL)..........................................259
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FIGURE 40 - OUTPUT CELL (OUT_CELL)...................................................258
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FIGURE 38 - TAP CONTROLLER FINITE STATE MACHINE .......................254
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FIGURE 36 - PRGD PATTERN GENERATOR ..............................................248
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FIGURE 35 - TELECOM LINE LOOPBACK DIAGRAM ................................221
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FIGURE 33 - DS2 LOOPBACK DIAGRAM....................................................219
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FIGURE 31 - DS3/E3 DIAGNOSTIC LOOPBACK DIAGRAM .......................218
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FIGURE 30 - T1/E1 DIAGNOSTIC DIGITAL LOOPBACK .............................217
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FIGURE 29 - T1/E1 LINE LOOPBACK..........................................................216
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FIGURE 28 - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ......207
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FIGURE 27 - TYPICAL DATA FRAME...........................................................207
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FIGURE 26 - CRCE COUNT VS. BER (T1 SF MODE) .................................200
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FIGURE 25 - CRCE COUNT VS. BER (T1 ESF MODE)...............................199
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07
:4
FIGURE 23 - CRCE COUNT VS. BER (E1 MODE) ......................................198
3:
25
FIGURE 22 - FER COUNT VS. BER (E1 MODE) .........................................197
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
FIGURE 47 - RECEIVE UNIPOLAR E3 STREAM.........................................265
FIGURE 60 - FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM........271 FIGURE 61 - FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM WITH TGAPCLK 271
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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FIGURE 62 - FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM ......272 FIGURE 63 - FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM WITH RGAPCLK 272
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FIGURE 59 - FRAMER MODE G.751 E3 RECEIVE OUTPUT STREAM WITH RGAPCLK 270
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FIGURE 58 - FRAMER MODE G.751 E3 RECEIVE OUTPUT STREAM ......270
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FIGURE 57 - FRAMER MODE G.751 E3 TRANSMIT INPUT STREAM WITH TGAPCLK 270
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FIGURE 56 - FRAMER MODE G.751 E3 TRANSMIT INPUT STREAM........269
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FIGURE 55 - FRAMER MODE DS3 RECEIVE OUTPUT STREAM WITH RGAPCLK 269
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FIGURE 54 - FRAMER MODE DS3 RECEIVE OUTPUT STREAM ..............269
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FIGURE 53 - FRAMER MODE DS3 TRANSMIT INPUT STREAM WITH TGAPCLK 268
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FIGURE 52 - FRAMER MODE DS3 TRANSMIT INPUT STREAM ...............268
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FIGURE 51 - TRANSMIT UNIPOLAR E3 STREAM ......................................267
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FIGURE 50 - TRANSMIT BIPOLAR E3 STREAM .........................................267
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FIGURE 49 - TRANSMIT UNIPOLAR DS3 STREAM....................................266
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FIGURE 48 - TRANSMIT BIPOLAR DS3 STREAM ......................................266
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07
:4
FIGURE 46 - RECEIVE BIPOLAR E3 STREAM ...........................................265
3:
25
FIGURE 45 - RECEIVE UNIPOLAR DS3 STREAM ......................................264
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
xiv
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
FIGURE 65 - 19.44 MHZ TELECOM DROP BUS TIMING - LOCKED STS-1 SPES / AU3 VCS.............................................................................................274
FIGURE 72 - SBI DROP BUS T1/E1 FUNCTIONAL TIMING ........................281 FIGURE 73 - SBI DROP BUS DS3/E3 FUNCTIONAL TIMING .....................282 FIGURE 74 - SBI ADD BUS JUSTIFICATION REQUEST FUNCTIONAL TIMING 283 FIGURE 75 - EGRESS 8.192 MBIT/S H-MVIP LINK TIMING .......................284
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
FIGURE 80 - MICROPROCESSOR INTERFACE READ TIMING.................293 FIGURE 81 - MICROPROCESSOR INTERFACE WRITE TIMING ...............295 FIGURE 82 - RSTB TIMING..........................................................................296
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FIGURE 79 - INGRESS FLEXIBLE BANDWIDTH PORT FUNCTIONAL TIMING287
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FIGURE 78 - EGRESS FLEXIBLE BANDWIDTH PORT FUNCTIONAL TIMING - SBI MASTER................................................................................................286
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FIGURE 77 - EGRESS FLEXIBLE BANDWIDTH PORT FUNCTIONAL TIMING - SBI SLAVE 286
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FIGURE 76 - INGRESS 8.192 MBIT/S H-MVIP LINK TIMING ......................285
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FIGURE 71 - REMOTE SERIAL ALARM PORT TIMING...............................281
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FIGURE 70 - 77.76 TELECOM ADD BUS TIMING........................................279
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FIGURE 69 - 19.44 MHZ TELECOM ADD BUS TIMING - LOCKED AU4 VC CASE 278
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FIGURE 68 - 19.44 MHZ TELECOM ADD BUS TIMING - LOCKED STS-1 SPES / AU3 VCS.............................................................................................277
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FIGURE 67 - 77.76 MHZ TELECOM DROP BUS TIMING ...........................276
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FIGURE 66 - 19.44 MHZ TELECOM DROP BUS TIMING - AU4 VC ............275
04
07
:4
3:
FIGURE 64 - 19.44 MHZ TELECOM DROP BUS TIMING - STS-1 SPES / AU3 VCS 273
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
xv
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
FIGURE 86 - TELECOM BUS AND LINE SIDE SBI OUTPUT TIMING.........306
FIGURE 98 - JTAG PORT INTERFACE TIMING...........................................319 FIGURE 99 - 324 PIN PBGA 23X23MM BODY.............................................321
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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FIGURE 97 - REMOTE SERIAL ALARM PORT TIMING...............................317
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FIGURE 96 - TRANSMIT LINE INTERFACE TIMING ...................................316
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FIGURE 95 - XCLK INPUT TIMING ..............................................................315
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FIGURE 94 - H-MVIP INGRESS DATA TIMING ............................................315
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FIGURE 93 - H-MVIP EGRESS DATA & FRAME PULSE TIMING................314
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FIGURE 92 - INGRESS FLEXIBLE BANDWIDTH PORT TIMING ................312
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FIGURE 91 - EGRESS FLEXIBLE BANDWIDTH PORT TIMING ................. 311
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FIGURE 90 - SBI SYSTEM SIDE DROP BUS COLLISION AVOIDANCE TIMING 310
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FIGURE 89 - SBI SYSTEM SIDE DROP BUS TIMING .................................310
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FIGURE 88 - SYSTEM SIDE SBI ADD BUS TIMING ....................................308
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FIGURE 87 - TELECOM BUS AND LINE SIDE SBI TRISTATE OUTPUT TIMING 306
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FIGURE 85 - LINE SIDE TELECOM BUS AND LINE SIDE SBI INPUT TIMING 304
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FIGURE 84 - DS3/E3 RECEIVE INTERFACE TIMING .................................301
3:
25
FIGURE 83 - DS3/E3 TRANSMIT INTERFACE TIMING ...............................298
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
xvi
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TABLE 6 TABLE 7 TABLE 8 TABLE 9 TABLE 10 TABLE 11 TABLE 12 TABLE 13 TABLE 14 TABLE 15 TABLE 16
- DS3 AIS FORMAT....................................................................133
- DS3 SYNCHRONIZER BIT STUFFING ALGORITHM. ............140
- INDEXING FOR 1.544 MBIT/S TRIBUTARIES........................187
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TABLE 18 OPTIONS TABLE 19 TABLE 20
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TABLE 17 OPTIONS
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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- 77.76 SBI AND TELECOM BUS ALIGNMENT OPTIONS........189 - TVT CONSTRAINTS FOR 77.76MHZ .....................................190
- 19.44 MHZ SBI TO 77.76 MHZ TELECOM TO BUS ALIGNMENT 190 - 77.76 MHZ SBI TO 19.44 MHZ TELECOM TO BUS ALIGNMENT 191 - PMON COUNTER SATURATION LIMITS (E1 MODE) ............196 - PMON COUNTER SATURATION LIMITS (T1 MODE) ............196
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- INDEXING FOR 2.048 MBIT/S TRIBUTARIES........................188
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- BOUNDARY SCAN REGISTER ..............................................180
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- IDENTIFICATION REGISTER .................................................179
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- INSTRUCTION REGISTER .....................................................179
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- REGISTER MEMORY MAP.....................................................148
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- DS3 DESYNCHRONIZER CLOCK GAPPING ALGORITHM...135
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TABLE 5
- ASYNCHRONOUS DS3 MAPPING TO STS-1 (STM-0/AU3) ..132
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TABLE 4
- ASYNCHRONOUS E1 TRIBUTARY MAPPING.......................130
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TABLE 3
- ASYNCHRONOUS T1 TRIBUTARY MAPPING .......................129
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04
TABLE 2
- PATH SIGNAL LABEL MISMATCH STATE ..............................127
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TABLE 1
- E1 FRAMER FRAMING STATES...............................................90
:4
3:
xvii
LIST OF TABLES
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TABLE 24 TABLE 25 TABLE 26 TABLE 27 TABLE 28 TABLE 29 TABLE 30 TABLE 31 TABLE 32 TABLE 33 TABLE 34 TABLE 35 TABLE 36 TABLE 37 TABLE 38
- STRUCTURE FOR CARRYING MULTIPLEXED LINKS..........223 - T1/TVT1.5 TRIBUTARY COLUMN NUMBERING ....................223
- SBI T1/E1 CLOCK RATE ENCODING.....................................227
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TABLE 40 TABLE 41 TABLE 42 TABLE 43
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TABLE 39
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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- DS3 BLOCK FORMAT .............................................................235 - DS3 MULTI-FRAME STUFFING FORMAT ..............................236 - E3 FRAMING FORMAT ...........................................................237 - E3 FRAME STUFFING FORMAT ............................................238 - TRANSPARENT VT1.5/TU11 FORMAT...................................239 - TRANSPARENT VT2/TU12 FORMAT.....................................242 - DATA AND CAS T1 H-MVIP FORMAT .....................................244 - DATA AND CAS E1 H-MVIP FORMAT.....................................245
xviii
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- DS3 FRAMING FORMAT.........................................................235
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- E1 CHANNEL ASSOCIATED SIGNALING BITS......................234
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- E1 FRAMING FORMAT ..........................................................232
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- T1 CHANNEL ASSOCIATED SIGNALING BITS......................231
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- T1 FRAMING FORMAT ...........................................................229
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- DS3 CLOCK RATE ENCODING ..............................................228
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- DS3 LINK RATE INFORMATION .............................................228
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- SBI T1/E1 LINK RATE INFORMATION....................................227
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- E1/TVT2 TRIBUTARY COLUMN NUMBERING.......................224
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TABLE 23
- PERFORMANCE REPORT MESSAGE CONTENTS ..............215
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TABLE 22
- PERFORMANCE REPORT MESSAGE STRUCTURE NOTES214
:4
3:
TABLE 21 - PERFORMANCE REPORT MESSAGE STRUCTURE AND CONTENTS 213
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TABLE 46 TABLE 47 TABLE 48 TABLE 49 TABLE 50 TABLE 51 TABLE 52 TABLE 53
- REPETITIVE PATTERN GENERATION (PS BIT = 1)..............251
TABLE 59 - SYSTEM SIDE SBI DROP BUS TIMING - 19.44 MHZ (FIGURE 86 AND FIGURE 89) .......................................................................................308 TABLE 60 - SYSTEM SIDE SBI DROP BUS TIMING - 77.76 MHZ (FIGURE 89 TO FIGURE 90) ..........................................................................................309
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TABLE 61 TABLE 62
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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TABLE 58
- SYSTEM SIDE SBI ADD BUS TIMING - 77.76 MHZ (FIGURE 88)307
- EGRESS FLEXIBLE BANDWIDTH PORT TIMING (FIGURE 91) 311 - INGRESS FLEXIBLE BANDWIDTH PORT TIMING (FIGURE 92) 311
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TABLE 57
- SYSTEM SIDE SBI ADD BUS TIMING - 19.44 MHZ (FIGURE 88)306
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TABLE 56 - TELECOM BUS OUTPUT TIMING - 77.76 MHZ (FIGURE 86 AND FIGURE 87) ............................................................................................305
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TABLE 55 - TELECOM BUS AND LINE SIDE SBI OUTPUT TIMING 19.44 MHZ (FIGURE 86 AND FIGURE 87) .....................................................305
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TABLE 54 - LINE SIDE TELECOM BUS AND LINE SIDE SBI INPUT TIMING - 19.44 MHZ (FIGURE 88) ..............................................................................303
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- DS3/E3 RECEIVE INTERFACE TIMING .................................300
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- DS3/E3 TRANSMIT INTERFACE TIMING ...............................296
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- RSTB TIMING..........................................................................296
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- MICROPROCESSOR INTERFACE WRITE ACCESS .............294
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- MICROPROCESSOR INTERFACE READ ACCESS...............292
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- D.C. CHARACTERISTICS .......................................................289
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- ABSOLUTE MAXIMUM RATINGS ...........................................288
04
07
:4
TABLE 45
- PSEUDO RANDOM PATTERN GENERATION (PS BIT = 0)...250
3:
25
TABLE 44
- CCS AND TS0 H-MVIP FORMAT ............................................246
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
xix
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TABLE 65 TABLE 66 TABLE 67 TABLE 68 TABLE 69
- XCLK INPUT (FIGURE 95) ......................................................315
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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- ORDERING INFORMATION....................................................320
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- JTAG PORT INTERFACE ........................................................318
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- REMOTE SERIAL ALARM PORT TIMING...............................317
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- TRANSMIT LINE INTERFACE TIMING (FIGURE 96) .............316
04
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:4
TABLE 64
- H-MVIP INGRESS TIMING (FIGURE 94) ...............................314
3:
25
TABLE 63
- H-MVIP EGRESS TIMING (FIGURE 93) ................................312
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
xx
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* *
Eight T1 modes of operation:
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Up to 84 T1 streams M13 multiplexed into three serial DS3 streams.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Four E1 modes of operation:
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Up to 84 DS3 multiplexed T1 streams are mapped as bit asynchronous VT1.5 virtual tributaries or TU-11 tributary units, providing a transmultiplexing ("transmux") function between DS3 and SONET/SDH. Up to 63 T1 streams mapped as bit asynchronous TU-12 tributary units into three STM-1/VC3 or TUG3 from a STM-1/VC4.
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DS3 M13 Multiplexer with ingress or egress per link monitoring.
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Up to 84 T1 streams M13 multiplexed into three DS3s, the DS3s are asynchronously mapped into three STS-1/STM-0 SPEs.
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Three STS-1, AU3 or TUG3 Bit Asynchronous VT1.5 or TU-11 Mappers with ingress or egress per tributary link monitoring.
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Up to 84 T1 streams mapped as byte synchronous VT1.5 virtual tributaries into three STS-1 SPEs or TU-11 tributary units into three STM-1/VC3 or TUG3 from a STM-1/VC4.
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Up to 84 T1 streams mapped as bit asynchronous VT1.5 virtual tributaries into three STS-1 SPEs or TU-11 tributary units into three STM-1/VC3 or TUG3 from a STM-1/VC4.
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Each SPE/DS3 independently programmable to allow the following modes of operation:
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Integrates 84 T1/E1 framers, three SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous or byte synchronous mappers, three full featured M13 multiplexers with DS3 framers, three E3 framers, and three SONET/SDH DS3 mappers in a single monolithic device for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams.
:4
3:
1
FEATURES
25
1
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Supports insertion and extraction of arbitrary rate (eg. fractional DS3) data streams to and from the SBI bus interface. Provides jitter attenuation in the T1 or E1 receive and transmit directions.
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Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface for high density system side device interconnection of up to 84 T1 streams, 63 E1 streams, 3 DS3 streams or 3 E3 streams. This interface also supports transparent virtual tributaries when used with the SONET/SDH mapper.
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Supports 8 Mbit/s H-MVIP on the system interface for all T1 or E1 links, a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels.
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Up to 84 VT1.5/TU11 or 63 VT2/TU12 tributaries can be passed between the line SONET/SDH bus and the system SBI bus as transparent virtual tributaries with pointer processing.
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Standalone unchannelized E3 framer mode (ITU-T Rec. G.751) for access to the entire E3 payload.
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Up to three DS3 streams are mapped bit asynchronously into VC-3s. The VC-3s are aligned within AU-3s.
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Standalone unchannelized DS3 framer mode for access to the entire DS3 payload.
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Two unchannelized DS3 modes of operation:
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Up to 63 E1 streams multiplexed into three DS3s following the ITU-T G.747 recommendation.
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Three STS-1, AU3 or TUG3 Bit Asynchronous VT2 or TU-12 Mappers with ingress or egress per tributary link monitoring.
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Up to 63 E1 streams mapped as byte synchronous VT2 virtual tributaries into three STS-1 SPE or TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4.
04
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3:
25
*
Up to 63 E1 streams mapped as bit asynchronous VT2 virtual tributaries into three STS-1 SPE or TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
2
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* *
Supports the M23 and C-bit parity DS3 formats. When configured to operate as a DS3 or E3 Framer, gapped transmit and receive clocks can be optionally generated for interface to link layer devices which only need access to payload data bits. DS3 or E3 Transmit clock source can be selected from either an external oscillator or from the receive side clock (loop-timed). Provides a SONET/SDH Add/Drop bus interface with integrated VT1.5, TU11, VT2 and TU-12 mapper for T1and E1 streams. Also provides a DS3 mapper. Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring. Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. Low power 1.8V/3.3V CMOS technology. All pins are 5V tolerant.
* * *
Each one of 84 T1 receiver sections:
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Frames to DS-1 signals in SF, SLC96 and ESF formats. Frames to TTC JT-G.704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation for Japanese applications.
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324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial temperature range (-40oC to 85oC) operation.
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Also provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and O.152.
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Provides an on-board programmable binary sequence generator and detector for error testing at DS3 and E3 rates. Includes support for patterns recommended in ITU-T O.151.
07
*
Provides per link diagnostic and line loopbacks.
:4
3:
25
*
Provides three independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
3
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* * * * *
Provides Inband Loopback Code generation and detection. Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Line side interface is either from the DS3 interface via the M13 multiplex or from the SONET/SDH Drop bus via the VT1.5, TU-11, VT2 or TU-12 demapper. Line side interface can also be configured as SBI bus. System side interface is either H-MVIP or SBI bus. Frames in the presence of and detects the "Japanese Yellow" alarm. Supports the alternate CRC-6 calculation for Japanese applications.
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*
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A pseudo-random sequence user selectable from 27 -1, 211 -1, 215 -1 or 220 - 1, may be detected in the T1 stream in either the ingress or egress directions. The detector counts pattern errors using a 16-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire T1 or any combination of DS0s within a framed T1.
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Provides DS-1 robbed bit signaling extraction and insertion, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a perchannel basis.
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co
n
*
Provides an optional elastic store which may be used to time the ingress streams to a common clock and frame alignment in support of a H-MVIP interface.
Tu
es
Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
da
y,
14
Se
Provides an HDLC interface with 127 bytes of buffering for terminating the facility data link.
pt
em
be
r,
20
04
Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link.
07
:4
*
Supports RAI-CI and AIS-CI alarm detection and generation.
3:
25
4
*
Provides Red, Yellow, and AIS alarm integration.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* * * * *
V5.2 link indication signal detection.
*
*
by
ad
ed
*
Do wn lo
*
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
Co
A pseudo-random sequence user selectable from 27 -1, 211 -1, 215 -1 or 220 - 1, may be detected in the E1 stream in either the ingress or egress directions. The detector counts pattern errors using a 16-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire E1 or any combination of timeslots within the framed E1. Line side interface is from the SONET/SDH Drop bus via the VT2 or TU-12 demapper. Line side interface can also be configured as SBI bus. System side interface is either H-MVIP or SBI bus.
nt e
nt Te a
Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels.
m
of P
ar
*
Can be programmed to generate an interrupt on change of signaling state.
tm
in
er
In
*
Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16.
co
n
*
Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction.
Tu
es
Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
da
y,
14
Se
pt
Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233.
em
be
r,
Provides an HDLC interface with 127 bytes of buffering for terminating the national use bit data link.
20
04
Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications.
07
:4
Each one of 63 E1 receiver sections:
3:
25
*
Provides external access for up to three de-jittered recovered T1 clocks.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
5
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* * * * * *
Provides transparency for the F-bit to support SLC96 data link insertion.
*
*
ed
by
Each one of 63 E1 transmitter sections: * Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
Co
System side interface is either H-MVIP or SBI bus.
nt e
Line side interface is through either DS3 Interface via the M13 multiplex or the SONET/SDH Add bus via the VT1.5, TU-11, VT2 or TU-12 mapper. Line side interface can also be configured as SBI bus.
nt Te a
A pseudo-random sequence user selectable from 27 -1, 211 -1, 215 -1 or 220 - 1, may be inserted into the T1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire T1 or any combination of DS0s within the framed T1.
m
of P
ar
tm
Supports the alternate ESF CRC-6 calculation for Japanese applications.
in
er
Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter.
In
co
Provides a digital phase locked loop for generation of a low jitter transmit clock.
n
Tu
Autonomously transmits an ESF Performance Report Message each second.
es
da
y,
14
*
Supports transmission of the alarm indication signal (AIS) or the Yellow alarm signal in SF, SLC96 and ESF formats.
Se
pt
*
Provides a 128 byte buffer to allow insertion of the facility data link using the host interface.
em
be
*
Provides minimum ones density through Bell (bit 7), GTE or "jammed bit 8" zero code suppression on a per-DS0 basis.
r,
20
04
07
*
May be timed to its associated receive clock (loop timing) or may derive its timing from the data rate received at the system interface or a common transmit clock; the transmit line clock may be synthesized from an N*8 kHz reference.
:4
Each one of 84 T1 transmitter sections:
3:
25
*
Provides external access for up to three de-jittered recovered E1 clocks.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
6
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* *
*
System side interface is either H-MVIP or SBI bus.
*
by
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
*
Co
Any sub-set of DS0s within a tributary may be selected.
Provides programmable pseudo-random test sequence generation (up to 2321 bit length sequences conforming to ITU-T O.151 standards) or any repeating pattern up to 32 bits. Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7.
nt e
*
Each generator and detector pair may be associated with any one of the 84 T1s or 63 E1s.
nt Te a
Six full featured T1/E1 Pattern Generators and Detectors:
m
of P
ar
*
Line side interface is through the SONET/SDH Add bus via the VT2 or TU-12 mapper. Line side interface can also be configured as SBI bus.
tm
in
er
*
Supports transmission of the alarm indication signal (AIS) and the remote alarm indication (RAI) signal.
In
co
*
Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233
n
Tu
*
Optionally inserts a datalink in the E1 national use bits.
es
da
y,
14
*
A pseudo-random sequence user selectable from 27 -1, 211 -1, 215 -1 or 220 - 1, may be inserted into the E1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire E1 or any combination of timeslots within the framed E1.
Se
pt
*
Provides a digital phase locked loop for generation of a low jitter transmit clock.
em
be
Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels.
r,
20
04
Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per channel basis.
07
:4
*
Supports unframed mode and framing bit, CRC, or data link by-pass.
3:
25
7
*
Transmits G.704 basic and CRC-4 multiframe formatted E1.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ad
ed
by
* *
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
Co
Allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under software control. Allows software to force the AIS insertion on a per tributary basis.
nt e
*
Calculates and compares the tributary path BIP-2 error detection code for each tributary and configurable to accumulate the BIP-2 errors on block or bit basis in internal registers.
nt Te a
*
Detects assertion and removal of tributary extended remote defect indications (RDI) for each tributary and optionally generates interrupts.
m
of P
*
Detects tributary path signal label unstable alarms (PSLU) and return to stable state for each tributary and optionally generates interrupts.
ar
tm
in
*
Provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (PSLM) and return to matched state for each tributary and optionally generates interrupts.
er
In
co
*
Detects tributary elastic store underflow and overflow and optionally generates interrupts.
n
Tu
*
Detects tributary path alarm indication signal (AIS) and return to normal state for each tributary and optionally generates interrupts
es
da
y,
*
Detects loss of pointer (LOP) and re-acquisition for each tributary and optionally generates interrupts.
14
Se
pt
*
Optionally frames to the H4 byte in the path overhead to determine tributary multi-frame boundaries and generates change of loss-of-frame status interrupts.
em
be
r,
*
Compensates for pleisiochronous relationships between incoming and outgoing higher level (STS-1, AU4, AU3) synchronous payload envelope frame rates through processing of the lower level tributary pointers.
20
04
*
Seamlessly interfaces with 77.76 MHz Drop and 77.76 MHz Add buses.
07
:4
*
Interfaces with a byte wide Telecom Add/Drop bus, interfacing directly with the PM5362 TUPP-PLUS and PM5342 SPECTRA-155 at 19.44 MHz.
3:
25
8
Each one of three SONET/SDH Tributary Path Processing Sections:
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
*
ed
by
* *
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
Co
Sets all fixed stuff bits for asynchronous mappings to zeros or ones per microprocessor control Extracts up to 28 bit asynchronous mapped VT1.5 virtual tributaries from an STS-1 SPE into T1 streams via an optional elastic store.
nt e
Bit asynchronous mapping assigns stuff control bits for all streams independently using an all digital control loop. Stuff control bits are dithered to produce fractional mapping jitter at the receiving desynchronizer.
nt Te a
m
*
Processes the tributary trace message (J2) of the tributaries carried in each STS-1/TUG-3 synchronous payload envelope.
of P
ar
*
Inserts up to 21 bit asynchronous mapped TU-12 tributary units into an STM1/VC4 TUG3 or STM-1/VC3 from E1 or T1 streams.
tm
in
*
Inserts up to 21 bit asynchronous mapped VT2 virtual tributaries into an STS1 SPE from E1 streams.
er
In
co
n
*
Inserts up to 28 byte synchronous mapped VT1.5 virtual tributaries into an STS-1 SPE or TU-11 tributary units into an STM-1/VC3 or TUG3 from a STM1/VC4.
Tu
es
*
Inserts up to 28 bit asynchronous mapped TU-11 tributary units into a STM1/VC4 TUG3 or STM-1/VC3 from T1 streams.
da
y,
14
*
Inserts up to 28 bit asynchronous mapped VT1.5 virtual tributaries into an STS-1 SPE from T1 streams.
Se
Each one of three SONET/SDH VT/TU Mapper Sections:
pt
em
Calculates and inserts the tributary path BIP-2 error detection code for each tributary.
be
*
r,
20
*
Support in-band error reporting by updating the FEBE, RDI and RFI bits in the V5 byte with the status of the incoming stream and remote alarm pins.
04
07
*
Inserts valid pointers and all-zeros transport overhead bytes on the outgoing Telecom Add bus, with valid control signals.
:4
3:
25
*
Inserts valid H4 byte and all-zeros fixed stuff bytes. Remaining path overhead bytes (J1, B3, C2, G1, F2, Z3, Z4, Z5) are set to all-zeros.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
9
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* *
*
Complies with DS3 to STS-1 asynchronous mapping standards.
*
ed
by
* *
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
Co
Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable. Provides indication of M-frame boundaries from which M-subframe boundaries and overhead bit positions in the DS3 stream can be determined by external processing.
nt e
Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
nt Te a
Each one of three DS3 Receiver Sections:
m
of P
ar
*
Performs majority vote C-bit decoding to detect stuff requests.
tm
in
*
Demapper ignores all transport overhead bytes, path overhead bytes and stuff (R) bits.
er
In
*
Extracts a DS3 stream from an STS-1 SPE (AU3).
co
n
*
Sets all fixed stuff (R) bits to zeros or ones per microprocessor control.
Tu
*
Maps a DS3 stream into an STS-1 SPE (AU3).
es
da
Each one of three SONET/SDH DS3 Mapper Sections:
y,
14
*
Performs majority vote C-bit decoding to detect stuff requests.
Se
pt
*
Demapper ignores all transport overhead bytes, path overhead bytes and stuff (R) bits.
em
be
Extracts up to 21 bit asynchronous mapped TU-12 tributary units from an STM-1/VC4 TUG3 or STM-1/VC3 into E1 or T1 streams via an optional elastic store.
r,
20
04
Extracts up to 21 bit asynchronous mapped VT2 virtual tributaries from an STS-1 SPE into E1 streams via an optional elastic store.
07
:4
3:
25
*
Extracts up to 28 bit asynchronous mapped TU-11 tributary units from an STM-1/VC4 TUG3 or STM-1/VC3 into T1 streams via an optional elastic store.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
10
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
*
* * *
Generates a B3ZS encoded 100... repeating pattern to aid in pulse mask testing.
by
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
Co
Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by internal register bits. Provides optional automatic insertion of far end receive failure (FERF) on detection of loss of signal (LOS), out of frame (OOF), alarm indication signal (AIS) or red alarm condition.
nt e
nt Te a
m
*
Provides B3ZS encoding.
of P
ar
*
Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface.
tm
in
*
Provides the overhead bit insertion for a DS3 stream.
er
In
Each one of three DS3 Transmit Sections:
co
n
Programmable pseudo-random test-sequence detection-(up to 232 -1 bit length patterns conforming to ITU-T O.151 standards) and analysis features.
Tu
es
da
y,
14
*
Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 128-byte deep FIFO buffer with programmable interrupt threshold. Supports polled or interrupt-driven operation. Selectable none, one or two address match detection on first byte of received packet.
Se
pt
*
Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
em
be
r,
20
04
*
Accumulates up to 65,535 line code violation (LCV) events per second, 65,535 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
07
*
Extracts valid X-bits and indicates far end receive failure (FERF).
:4
3:
25
*
Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
11
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* * * * * *
Allows per DS2 alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control. Allows DS2 alarm indication signal (AIS) to be activated or cleared in the demultiplex direction automatically upon loss of DS3 frame alignment or signal. Supports C-bit parity DS3 format.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
*
Co
nt e
nt Te a
m
Internally generates a DS2 clock for use in integrated M13 or C-bit parity multiplex applications. Alternatively accepts external DS2 clock reference.
of P
Allows insertion and detection of per DS2 payload loopback requests encoded in the C-bits to be activated under microprocessor control.
ar
tm
in
Includes required FIFO buffers for rate adaptation in the multiplex path.
er
In
Performs required bit stuffing/destuffing including generation and interpretation of C-bits.
co
n
*
Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream.
Tu
es
M23 Multiplexer Section:
da
y,
14
Se
pt
*
Provides programmable pseudo-random test sequence generation (up to 232-1 bit length sequences conforming to ITU-T O.151 standards) or any repeating pattern up to 32 bits. The test pattern can be framed or unframed. Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7.
em
be
*
Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled and interrupt-driven operation.
r,
20
04
*
Supports insertion of bit-oriented codes in the C-bit parity far end alarm and control channel.
07
:4
3:
25
*
Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error (FEBE) events.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
12
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
DS2 Transmitter Section: * * *
* * * * * *
Performs required bit stuffing including generation and interpretation of C-bits.
Performs required inversion of second and fourth multiplexed DS1 streams as required by ANSI T1.107 Section 7.2. Allows insertion and detection of per DS1 payload loopback requests encoded in the C-bits to be activated under microprocessor control. Allows per tributary alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
Includes required FIFO buffers for rate adaptation in the multiplex path.
nt Te a
m
Multiplexes four DS1 or three 2048 kbit/s (according to ITU-T Rec. G.747) bit streams into a single M12 format DS2 bit stream.
of P
ar
M12 Multiplexer Section:
tm
in
Provides optional automatic insertion of far end receive failure (FERF) on detection of out of frame (OOF), alarm indication signal (AIS) or red alarm condition.
er
In
co
Provides for transmission of far end receive failure (FERF) and alarm indication signal (AIS) under microprocessor control.
n
Tu
es
Generates the required X, F, and M bits into the transmitted DS2 bit stream. Allows inversion of inserted F or M bits for diagnostic purposes.
da
y,
14
Se
*
Accumulates up to 255 DS2 M-bit or F-bit error events per second.
pt
em
*
Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end receive failure (FERF).
be
r,
20
*
Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a 10-3 bit error rate.
04
07
:4
*
Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
3:
25
13
DS2 Framer Section:
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* *
Frames to G.751 and G.832 E3 unchannelized data streams.
*
*
ad
ed
by
*
Do wn lo
*
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
Co
Provides three 8 Mbit/s H-MVIP interfaces for common channel signaling (CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is available through this interface. In E1 mode timeslots 15, 16 and 31 are available through this interface. Optionally, timeslot 0 may be presented instead of timeslot 15. All links accessed via the H-MVIP interface will be synchronously timed to the common H-MVIP clock and frame alignment signals, CMV8MCLK, CMVFP, CMVFPC. H-MVIP access for Channel Associated Signaling is available with the Scaleable Bandwidth Interconnect bus as an optional replacement for CAS
nt e
nt Te a
m
of P
ar
*
Provides twenty one 8 Mbit/s H-MVIP interfaces for synchronous access to all channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The CAS bits occupy one nibble of every byte on the H-MVIP interfaces and are repeated over the entire T1 or E1 multi-frame.
tm
in
er
In
co
*
Provides twenty one 8 Mbit/s H-MVIP data interfaces for synchronous access to all the DS0s of all 84 T1 links or all timeslots of all 63 E1s. T1 DS0s are bundled from four T1 links in sequential order, 1-4, 5-8, 9-12, ..., 81-84. E1 timeslots are bundled from 4 E1 links in sequential order, 1-4, 5-8, 9-12, ..., 57-60 and 61-63.
n
Tu
Synchronous System Interfaces:
es
da
for G.832, the Trail Trace is inserted, and an integral HDLC transmitter is provided to insert either the Network Requirement or the General Purpose data link.
y,
14
Se
pt
*
Provides frame insertion for the G.751 or G.832 E3 applications, alarm insertion, and diagnostic features.
em
Each one of three E3 Transmit Sections:
be
r,
For G.832, terminates the Trail Trace and either the Network Requirement or the General Purpose data link.
20
04
07
:4
Each one of three E3 Framer Sections:
3:
14
25
*
Allows automatic tributary AIS to be activated upon DS2 out of frame.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* *
Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.
* * *
by
Transparent VT/TU access can be selected only when tributaries are mapped into SONET/SDH. Transparent VT1.5s and TU-11s can be selected on a per tributary basis in combination with framed and unframed T1s. Transparent VT2s and TU-12s can be selected on a per tributary basis in combination with framed and unframed E1s.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
Co
nt e
Synchronous access for T1 DS0 channels or E1 timeslots is supported in a locked format mode. Selectable on a per tributary basis.
nt Te a
m
*
Up to three arbitrary rate data streams inserted into and extracted from the SBI via bit serial ports.
of P
ar
*
Framed and unframed T1 access can be selected on a per T1 basis. Framed and unframed E1 access can be selected on a per E1 basis.
tm
in
er
In
co
*
External devices can access unframed DS3, framed unchannelized DS3, unframed E3, framed unchannelized E3, unframed (clear channel) T1s, framed T1s, unframed (clear channel) E1s, framed E1s, arbitrary rate clear channel data stream (eg. fractional DS3), transparent virtual tributaries or transparent tributary units over this interface.
n
Tu
es
*
System side SBI bus operates at either 19.44 MHz or 77.76 MHz. Line side SBI bus operates at 19.44MHz to communicate with PM4318 OCTLIU or PM4319 OCTLIU SH.
da
y,
14
Se
pt
*
Provides a high density byte serial interconnect for all framed and unframed TEMUX 84 links. Utilizes an Add/Drop configuration to asynchronously mutliplex up to 84 T1s, 63 E1s or 3 DS3s, with multiple payload or link layer processors. Line side and system side interfaces can be configured as SBI bus.
em
be
Scaleable Bandwidth Interconnect (SBI) Bus:
r,
20
04
Alarm status, T1 F-bit and inband signaling control is available using otherwise unused bit positions.
07
:4
access over the SBI bus as well as with the H-MVIP data interface. Common Channel Signaling H-MVIP access is available with the SBI bus, serial PCM and H-MVIP data interfaces.
3:
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
15
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
da
y,
14
Se
pt
em
be
r,
20
04
07
*
Transmit timing is mastered either by the TEMUX 84 or a layer 2 device connecting to the SBI bus. Timing mastership is selectable on a per tributary basis, where a tributary is either an individual T1, E1, E3 or a DS3.
:4
3:
25
*
Channel associated signaling bits for channelized T1 and E1 are explicitly identified across the bus.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
16
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* * * * * *
SONET/SDH Terminal Multiplexers
Digital Access Cross-Connect Systems
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
Optical Access Equipment
n
Tu
Channelized and Unchannelized DS3 Frame Relay Interfaces
es
C-Bit Parity Based M13 Multiplexer
da
y,
M23 Based M13 Multiplexer
14
Se
pt
*
SONET/SDH Add Drop Multiplexers
em
*
Frame Relay switches and access devices (FRADS)
be
r,
20
*
High density E1 interfaces for multiplexers, multi-service switches, routers and digital modems.
04
07
*
High density T1 interfaces for multiplexers, multi-service switches, routers and digital modems.
:4
3:
17
2
APPLICATIONS
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
*
* * *
Bell Communications Research - Alarm Indication Signal Requirements and Objectives, TR-TSY-000191 Issue 1, May 1986
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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ed
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Bell Communications Research - Wideband and Broadband Digital CrossConnect Systems Generic Criteria, TR-NWT-000233, Issue 3, November 1993
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nt e
Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit Functional Specification, TA-TSY-000147, Issue 1, October, 1987
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*
Bell Communications Research, TR-TSY-000009 - Asynchronous Digital Multiplexes Requirements and Objectives, Issue 1, May 1986
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American National Standard for Telecommunications - Integrated Services Digital Network (ISDN) Primary Rate- Customer Installation Metallic Interfaces Layer 1 Specification, ANSI T1.408-1990
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tm
*
in
er
*
American National Standard for Telecommunications - Customer Installation-toNetwork - DS3 Metallic Interface Specification, ANSI T1.404-1994
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*
American National Standard for Telecommunications - Carrier to Customer Installation - DS-1 Metallic Interface Specification, ANSI T1.403-1999
Tu
es
*
American National Standard for Telecommunications - Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring, ANSI T1.231-1997
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y,
14
*
American National Standard for Telecommunications - Digital Hierarchy - Formats Specification, ANSI T1.107-1995
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American National Standard for Telecommunications - ANSI T1.105.02 - "Synchronous Optical Network (SONET) - Payload Mappings," October 27, 1995.
pt
em
be
r,
20
*
American National Standard for Telecommunications - ANSI T1.105 - "Synchronous Optical Network (SONET) - Basic Description Including Multiplex Structure, Rates, and Formats," October 27, 1995.
04
07
*
American National Standard for Telecommunications - Digital Hierarchy Synchronous DS3 Format Specifications, ANSI T1.103-1993
:4
3:
18
3
REFERENCES
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* *
* *
ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates, May 1994
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
*
by
ETSI ETS 300 417-1-1 - "Transmission and Multiplexing (TM); Generic Functional Requirements for Synchronous Digital Hierarchy (SDH) equipment; Part 1-1: Generic processes and performance," January, 1996.
Co
nt e
*
ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at the Digital Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2 Interface Specification, September 1994.
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ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at the Digital Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1 Interface Specification, February, 1994.
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*
ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification and Test Principles, 1992.
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er
*
ITU Study Group XVIII - Report R 105, Geneva, 9-19 June 1992
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co
*
AT&T - Accunet T1.5 - Service Description and Interface Specification, TR 62411, December, 1990
n
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AT&T - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, TR 54016, September, 1989.
es
*
da
y,
14
*
Bell Communications Research - OTGR: Network Maintenance Transport Surveillance - Generic Digital Transmission Surveillance, TR-TSY-000820, Section 5.1, Issue 1, June 1990
Se
pt
*
Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue 5, December, 1993
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Bell Communications Research - Integrated Digital Loop Carrier Generic Requirements, Objectives, and Interface, TR-NWT-000303, Issue 2, December, 1992
r,
20
04
Bellcore GR-253-CORE - "SONET Transport Systems: Common Criteria," Issue 2, Revision 1, December 1997.
07
:4
3:
25
*
Bell Communications Research - Digital Interface Between The SLC96 Digital Loop Carrier System And A Local Digital Switch, TR-TSY-000008, Issue 2, August 1987
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
19
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
*
by
*
ITU-T Recommendation O.151 - Error Performance Measuring Equipment Operating at the Primary Rate and Above, October 1992 ITU-T Recommendation O.152 - Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and N x 64 kbit/s, October 1992
Co
nt e
*
ITU-T - Recommendation I.431 - Primary Rate User-Network Interface - Layer 1 Specification, 1993.
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*
ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Ex-hange (LE) - V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March 1995.
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*
ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Ex-hange (LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994.
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*
ITU-T Recommendation G.823, - The Control of Jitter and Wander within Digital Networks which are Based on the 2048 kbit/s Hierarchy, 03/94
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*
ITU-T Recommendation G.783 - Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks, April, 1997.
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es
*
ITU-T Recommendation G.775, - Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria, 11/94
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y,
*
ITU-T Recommendation G.747 - Second Order Digital Multiplex Equipment Operating at 6312 kbit/s and Multiplexing Three Tributaries at 2048 kbit/s, 1988
14
Se
*
ITU-T Recommendation G.707 - Network Node Interface for the Synchronous Digital Hierarchy, 1996
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em
ITU-T - Recommendation G.732 - Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s, 1993.
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*
r,
20
*
ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704 Frame Structures, 1991.
04
07
*
ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1995.
:4
3:
25
*
ETSI, Generic Functional Requirements for Synchronous Digital Hierarchy (SDH) Equipment, Jan 1996
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
20
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
*
GO-MVIP, H-MVIP Standard, Release1.1a, 1997
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
Co
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in
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In
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*
GO-MVIP, Multi-Vendor Integration Protocol, MVIP-90, Release 1.1, 1994
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es
*
Nippon Telegraph and Telephone Corporation - Technical Reference for HighSpeed Digital Leased Circuit Services, Third Edition, 1990.
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y,
14
*
TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 Specification, 1995.
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*
TTC Standard JT-G706 - Frame Synchronization and CRC Procedure
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em
TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital Interfaces, 1995.
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*
r,
20
*
International Organization for Standardization, ISO 3309:1984 - High-Level Data Link Control procedures - Frame Structure
04
07
*
ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer Specification, March 1993
:4
3:
25
*
ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error Performance at Bit Rates below the Primary Rate, October 1992.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
21
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
SBI FREEDM 84A672
APPI
04
07
Utopia
Utopia
Figure 1
- Any-Service-Any-Port Application
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Spectra 155
TEMUX 84
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AAL1gator32
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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Co
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nt Te a
m
of P
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In
Figure 1 illustrates how frame relay (FREEDM84A672), circuit emulation (AAL1gator32) and ATM inverse multiplexing (IMA84) may all be supported on the same port with a common SBI bus as the enabling technology.
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Telecom Bus
IMA
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APPI
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20
Packet/Cell Interworking Function
:4
3:
22
4
APPLICATION EXAMPLES
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
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TEMUX
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84
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TEMUX
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Spectra 622
84
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TEMUX
FREEDM 336
Interworking Function
Utopia
Packet/Cell
APPI
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84
20
TEMUX
04
APPI
07
Utopia
Telecom Bus
SBI
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3:
23
25
Figure 2
- High Density Frame Relay Application
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
FPGA
07
IFBWCLK IFBWEN
:4
RMFPO RDATO RSCLK
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DS3 LIU
TMFPO
TEMUX-84
EFBWDREQ
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14
Se
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Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
To support evolving fractional DS3 applications, flow-controlled ports provide access to SBI bus bandwidth. Several non-standard schemes have been devised to use a portion of the DS3 payload. Given that these protocols are subject to change, they are best supported by external programmable logic. Figure 3 illustrates one implementation. Other implementations and applications are possible. In the ingress direction, the framed DS3 is presented to an FPGA, whose responsibility it is to identify the utilitized bits of the payload. Valid bits are indicated to the Ingress Flexible Bandwidth Port via an enable signal, IFBWEN.
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44.736 MHz
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FPGA
EFBWDAT
EFBWCLK
EFBWEN
TMFPI
TICLK
TDATI
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IFBWDAT
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20
04
3:
SBI Bus
24
25
Figure 3
- Fractional DS3 Application
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
Co
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of P
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In the egress direction, an FPGA formats the payload of a DS3, while the TEMUX 84 inserts the DS3 frame overhead. The FPGA contains a data buffer. Based on the DS3 frame alignment dictated by the TMFPO signal, the FPGA inserts bits from the data buffer into the DS3 payload according to the protocol supported. To ensure the data buffer is replenished, the FPGA asserts the EFBWDREQ signal to initiate the transfer of a bit. The Egress Flexible Bandwidth Port responds by asserting EFWBEN coincident with EFWBDAT presenting valid data. The SBI Add bus participates by modulating its SAJUST_REQ output to match the SBI data rate to that required to keep internal FIFOs centered.
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be
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20
04
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3:
The bits are collected into bytes by the TEMUX 84 and inserted into the payload of the SBI Drop bus.
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
25
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LIUs
In
DS3/E3 Tx System I/F
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Figure 4
- TEMUX 84 Block Diagram
Egress Flexible B/W Port Egress H-MVIP T1/E1 JAT84 T1/E1 JAT84 T1/E1 TRAN84 T1/E1 FRMR84 T1/E1 ELST84
Telecom Bus EVTPP TTOP TRAP
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See Figure 10 for a block diagram of Transmux Mode.
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System side access to the T1s and E1s is available as Synchronous H-MVIP interfaces or the SBI bus. DS3 line side access is via the clock and data interface for line interface units (LIUs) or DS3 mapped into the SONET/SDH telecom bus. Unchannelized DS3 system side access is available through the SBI bus.
14
Se
pt
em
Figure 4 shows the complete TEMUX 84. T1 links can be multiplexed into the DS3s or can be mapped into the telecom bus as SONET VT1.5 virtual tributaries or as SDH TU-11 or TU-12 tributary units. E1 links can be mapped into the telecom bus as SONET VT2 virtual tributaries or as SDH TU-12 tributary units. Line side interface can also be configured as SBI bus.
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20
04
07
H-MVIP EXSBI System Side SBI Bus T1/E1 ELST84 INSBI T1/E1 SIGX84 Ingress H-MVIP H-MVIP Ingress Flexible B/W Port
5.1
Top Level Block Diagram
INSBI (byte)
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Line Side SBI Bus
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TTMP (bit)
IVTPP Telecom Bus D3MD
DS3/E3 FRMR
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RTOP/ RTTB
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RTDM (bit) EXSBI (byte)
M13
PISO
LIUs
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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nt e
DS3/E3 Rx System I/F
:4
3:
26
5
BLOCK DIAGRAM
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Se
Figure 5
LIUs
M 13 M 13 DS3 TRAN
- M13 Multiplexer Block Diagram
PISO T1/E1 JAT84 T1/E1 JAT84
pt
em
Figure 5 shows the TEMUX 84, configured as a M13 multiplexer, connected to a synchronous H-MVIP system side bus. In this example the TEMUX 84 provides synchronous access to the fully channelized T1s (access to all DS0s) multiplexed into the DS3. There is also synchronous H-MVIP access to all channel associated signaling channels (CAS). Additional H-MVIP interfaces can be used to provide synchronous access to the common channel signaling channels (CCS), although this same information is available within the data H-MVIP signals.
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20
04
07
:4
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T1/E1 TRAN84 T1/E1 FRM R84
14
M 13 M 13 M 13
3:
T1/E1 ELST84 T1/E1 ELST84 Egress H-M VIP
5.2
M13 Multiplexer Mode Block Diagram
25
H-M VIP
T1/E1 SIGX84 Ingress H-M VIP
SIPO
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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in
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In
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LIUs
M 13 M 13 DS3 FRM R
M 13 M 13 M 13
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
H-M VIP
27
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
y,
M13 M13 VTPP
TTOP
TRAP
INSBI
14
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M13 M13 VTPP
M13 M13 RTOP/ RTTB
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Telecom Bus
TTMP (bit)
Se
Figure 6
- VT/TU Mapper Block Diagram
pt
em
Figure 6 shows the TEMUX 84 configured as a VT or TU mapper. In this mode the TEMUX 84 bypasses the T1 and E1 framers and provides access for up to 84 independent unframed 1.544 Mbit/s streams or 63 independent unframed 2.048 Mbit/s streams. The 1.544 Mbit/s and 2.048 Mbit/s streams can be accessed on the system side via the SBI bus. The T1 or E1 framers can be used to monitor the passing traffic in either the ingress or egress direction. The M13 Multiplexer mode operates in much the same way as the VT and TU mapper shown in Figure 6.
T1/E1 JAT84 T1/E1 JAT84
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20
04
07
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3:
EXSBI T1/E1 FRMR84 INSBI
5.3
VT/TU Mapper Only Mode Block Diagram
25
SBI 155
RTDM (bit) EXSBI
28
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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in
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In
co
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Tu
TIC LK TCLK TPOS/TDAT TNEG/TM FP
B3ZS/ HDB3 Encode
TRAN DS3/E3 Tran sm it Fram er FRM R DS3/E3 R eceive Fram er PM ON Perf. M onitor
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TDPR Tx HDLC
14
Se
pt
Figure 7
- DS3/E3 Framer Only Mode Block Diagram
em
Figure 7 shows the TEMUX 84 configured as a DS3 or E3 framer. In this mode the TEMUX 84 provides access up to three full DS3/E3 unchannelized payloads. The payload access (right side of diagram) has two clock and data interfacing modes, one utilizing a gapped clock to mask out the DS3/E3 overhead bits and the second utilizing an ungapped clock with overhead indications on a separate overhead signal. The SBI bus can also be used to provide access to the unchannelized DS3/E3.
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RCLK/VCLK RPOS/RDAT RNEG/RLCV
B3ZS/ HDB3 Decod e
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RDLC Rx HDLC
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5.5
T1/E1 FDL Extraction/Insertion and Alarm/Error Response Figure 8 below shows the positioning and interaction of the TXFRMR and RXFRMR when the TEMUX 84 is configured for High Density Framer mode. The TXFRMR can insert HDLC PRM messages via software with the THDL. It can also insert PRM messages automatically based upon the information gathered by the RXFRMR. The RXFRMR collects the T1/E1 receieved PMON data and optionally sends this information to the TXFRMR. The RXFRMR also sends the received HDLC stream to the RDHL for PRM processing. Figure 8 also shows the RXFRMR sending reponse indications to the TXFRMR informing it when to
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
Co
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3X
04
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TDA TI TFPO/TM FPO/TGAPC LK TFP I/T M FP I RGAPCLK/RSCLK RDATO RFPO/RMFPO ROVRHD
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3:
29
5.4
DS3/E3 Framer Only Block Diagram
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
04
07
HDLC Receiver (PRM Processing) RHDL
Figure 8
- High Density Framer Mode T1/E1 Block Diagram
pt
RJAT
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From SONET/SDH Demappers or M13 Demux from Line Side
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14
T1/E1 Receive Framer RXFRMR
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20
To SIGX/RXELST/RPCC and System side
:4
3:
insert the T1 Yellow alarm, E1 FEBEs (E bits) and the E1 RAI Alarm (A bit) towards the line side.
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
In
co
n
E1 E/A bit and T1 Yellow Alarm Response Indication
Tu
es
APRM Data
da
tm
To SONET/SDH Mappers or M13 Mux to Line Side
TJAT
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
Figure 9 shows the T1/E1 PMON and FDL extraction block diagram when the TEMUX 84 is configured for Mapper/Multiplexer mode. In this mode the T1/E1 data is carried clear channel bi-directionally between the line side and the system side. There is the ability to collect T1/E1 PMON, via the RXFRMR and extract the FDL, via the RHDL in either direction, but only one direction at a time. The TXPMON bit of the RJAT Indirect Channel Data Register selects chooses the direction of the PMON and FDL extraction. The TXFRMR is not available in this mode, thus FDL HDLC insertion is not possible, nor is the insertion of T1 Yellow, E1 FEBEs or E1 RAI.
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T1/E1 Transmit Framer TXFRMR
in
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HDLC Transmitter (PRM Insertion) THDL
From TXELST/TPCC and System side
ar
30
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
From SONET/SDH Demappers or M13 Demux from Line Side
RJAT TXPMON bit
r,
20
To RPCC and System side
04
07
:4
TJAT
3: es da y, 14
T1/E1 Receive Framer RXFRMR
25
HDLC Receiver (PRM Processing) RHDL
31
Figure 9
- Mapper/Multiplexer Mode T1/E1 Block Diagram
To SONET/SDH Mappers or M13 Mux to Line Side
Se
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For more information on Transmux, see section 9.2.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
Co
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The TXFRMR is not available in this mode, thus FDL HDLC insertion is not possible, nor is the insertion of T1 Yellow, E1 FEBEs or E1 RAI.
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Figure 10 below shows the T1/E1 PMON and FDL extraction block diagram when the TEMUX 84 is configured for Transmux mode. In this mode the T1/E1 data is carried clear channel bi-directionally between the DS3 M13 Mulitplexers and the T1/E1 Mappers. There is the ability to collect T1/E1 PMON, via the RXFRMR and extract the FDL, via the RHDL in either direction, but only one direction at a time. The TXPMON bit of the RJAT Indirect Channel Data Register selects chooses the direction of the PMON and FDL extraction.
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In
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Tu
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From TPCC and System side
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
20
From SONET/SDH Demappers
TXPMON bit
04
TJAT
07
To DS3 M13 Muliplexer
:4 er In co n Tu es da y,
RJAT
To SONET/SDH Mappers
3: 14 Se pt
T1/E1 Receive Framer RXFRMR
25
HDLC Receiver (PRM Processing) RHDL
Figure 10
- Transmux Mode T1/E1 Block Diagram
From DS3 M13 Demultiplexer
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
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nt Te a
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in
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be
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AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
32
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ad
ed
In the ingress direction, each of the 84 T1 links is either demultiplexed from a channelized DS3 or extracted from SONET VT1.5, TU-11 or TU-12 mapped bus. Each T1 framer can be configured to frame to the common DS1 signal formats (SF, SLC96, ESF and Japanese variants) or to be bypassed (unframed mode). Each T1 framer detects the presence of Yellow and AIS patterns and also integrates Yellow, Red, and AIS alarms. T1 performance monitoring with accumulation of CRC-6 errors, framing bit errors, out-of-frame events, and changes of frame alignment is provided. The TEMUX
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
Co
nt e
nt Te a
Each of the T1 and E1 framers and transmitters is independently software configurable, allowing timing master and feature selection without changes to external wiring. T1 and E1 tributaries may be mixed at a VC-3/TUG-3/DS3 granularity.
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The TEMUX 84 can be used as a SONET/SDH VT/TU mapper or M13 multiplexer with performance monitoring in either the ingress or egress direction for up to 84 T1s or 63 E1s. In this configuration the T1 and E1 transmit framers are disabled and either the ingress or egress T1 or E1 signals are routed to the T1 or E1 framers for performance monitoring purposes, which include error event accumulation, alarm monitoring and HDLC termination.
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This device can also be configured as a DS3 or E3 framer, providing external access to the full DS3 or E3 payload, or a VT/TU mapper, providing access to unframed 1.544 Mbit/s and 2.048 Mbit/s links.
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The TEMUX 84 supports asynchronous multiplexing and demultiplexing of 84 DS1s or 63 E1s into three DS3 signals as specified by ANSI T1.107, Bell Communications Research TR-TSY-000009 and ITU-T Rec. G.747. It supports bit asynchronous or byte synchronous mapping and demapping of 84 T1s or 63 E1s into SONET/SDH as specified by ANSI T1.105, Bell Communications Research GR-253-CORE and ITU-T Recommendation G.707. The TEMUX 84 also supports mapping of 63 T1s into SDH via TU-12s. Up to 84 Transparent VT1.5s and TU-11s or 63 Transparent VT2s and TU-12s can be transferred between the SONET/SDH interface and the SBI bus interface.
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The PM8316 High Density T1/E1 Framer with Integrated VT/TU Mappers and M13 Multiplexers (TEMUX 84) is a feature-rich device for use in any applications requiring high density link termination over T1 and E1 (G.747) channelized DS3 or T1 and E1 channelized SONET/SDH facilities.
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DESCRIPTION
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
E1 performance monitoring with accumulation of CRC-4 errors, far end block errors and framing bit errors is provided. The TEMUX 84 provides a receive HDLC controller for the detection and termination of messages on the national use bits. Detection of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300-233 is supported. V5.2 link ID signal detection is also supported. An interrupt may be generated on any change of state of the Sa codewords. An elastic store for slip buffering and rate adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a per-channel basis. Receive side data and signaling trunk conditioning is also provided.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In the egress direction, framing is generated for 63 E1s into either a DS3 multiplex according to ITU-T Rec. G.747 or a SONET/SDH mapped add bus. Each E1 transmitter generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Transmission of the
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The E1 framers support detection of various alarm conditions such as loss of frame, loss of signaling multiframe and loss of CRC multiframe. The E1 framers also support reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal.
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In the ingress direction, each of the 63 E1 links is either demultiplexed from a DS3 according to ITU-T Rec. G.747 or extracted from SONET/SDH VT2 or TU-12 mapped bus. Each E1 framer detects and indicates the presence of remote alarm and AIS patterns and also integrates Red and AIS alarms.
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In the egress direction, framing is generated for 84 T1s into either a DS3 multiplex or a SONET/SDH mapped add bus. Each T1 transmitter frames to SF or ESF DS1 formats, or framing can be optionally disabled. The TEMUX 84 supports signaling insertion, idle code substitution, data insertion, line loopback, data inversion and zero-code suppression on a per-DS0 basis. PRBS generation and detection is supported on a framed and unframed T1 basis.
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84 also detects the presence of ESF bit oriented codes, and detects and terminates HDLC messages on the ESF data link. The HDLC messages are terminated in a 127 byte FIFO. An elastic store that optionally supports slip buffering and adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing and interrupt on signaling state change on a per-DS0 basis. The TEMUX 84 also supports inband loopback code generation and detection, idle code substitution, digital milliwatt code insertion, data link extraction, trunk conditioning, data sign and magnitude inversion, and pattern generation and detection on a per-DS0 basis.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
34
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In the DS3 receive direction, the TEMUX 84 frames to DS3 signals with a maximum average reframe time of 1.5 ms in the presence of 10-3 bit error rate and detects line code violations, loss of signal, framing bit errors, parity errors, Cbit parity errors, far end block errors, AIS, far end receive failure and idle code. The DS3 framer is an off-line framer, indicating both out of frame (OOF) and change of frame alignment (COFA) events. The error events (C-BIT, FEBE, etc.) are still indicated while the framer is OOF, based on the previous frame alignment. When in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are provided for Path Maintenance Data Link support. In addition, valid bit-oriented codes in the FEAC channels are detected and are available through the microprocessor port. Error event accumulation is also provided by the TEMUX 84. Framing bit errors, line code violations, excessive zeros occurrences, parity errors, C-bit parity errors, and far end block errors are accumulated. Error accumulation continues even while the off-line framers are indicating OOF. The counters are intended to
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When configured as a DS3 multiplexer/demultiplexer or DS3 framer, the TEMUX 84 accepts and outputs either digital B3ZS-encoded bipolar or unipolar signals compatible with M23 and C-bit parity applications.
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A Scaleable Bandwidth Interconnect (SBI) high density byte serial system interface provides higher levels of integration and dense interconnect. The SBI bus interconnects up to 84 T1s or 63 E1 both synchronously or asynchronously. The SBI allows transmit timing to be mastered by either the TEMUX 84 or link layer device connected to the SBI bus. In addition to framed T1s and E1s the TEMUX 84 can transport unframed T1 or E1 links and framed or unframed DS3 or E3 links over the SBI bus.
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In synchronous backplane systems, 8 Mbit/s H-MVIP interfaces are provided for access to 2016 DS0 channels, channel associated signaling (CAS) for all 2016 DS0 channels and common channel signaling (CCS) for all 84 T1s or 63 E1s (or combination thereof). The CCS signaling H-MVIP interface is independent of the DS0 channel and CAS H-MVIP access. The use of any of the H-MVIP interfaces requires that common clocks and frame pulse be used along with T1 slip buffers.
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The TEMUX 84 can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. Three jitter attenuated recovered T1/E1 clocks can be routed outside the TEMUX 84 for network timing applications.
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4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported. PRBS generation or detection is supported on a framed and unframed E1 basis.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
35
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
The TEMUX 84 also supports diagnostic options which allow it to insert, when appropriate for the transmit framing format, parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms. A Pseudo Random Binary Sequence (PRBS) can be inserted into a DS3 payload and checked in the receive DS3 payload for bit errors. A fixed 100100... pattern is available for insertion directly into the B3ZS encoder for proper pulse mask shape verification. The TEMUX 84 may be used as an E3 framer for the transport of framed but unchannelized E3 data streams complying to the ITU-T Recommendations G.751 or G.832. The line interface may be configured as either unipolar or HDB3encoded. When configured in DS3 multiplexer mode, seven 6312 kbit/s data streams are demultiplexed and multiplexed into and out of each DS3 signal. Bit stuffing and rate adaptation is performed. The C-bits are set appropriately, with the option of inserting DS2 loopback requests. Interrupts can be generated upon detection of loopback requests in the received DS3. AIS may be inserted in the any of the 6312 kbit/s tributaries in both the multiplex and demultiplex directions. C-bit parity is supported by sourcing a 6.3062723 MHz clock, which corresponds to a stuffing ratio of 100%.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Framing to the demultiplexed 6312 kbit/s data streams supports DS2 (ANSI TI.107) frame formats. The maximum average reframe time is 7ms for DS2. Far end receive failure is detected and M-bit and F-bit errors are accumulated. The DS2 framer is an off-line framer, indicating both OOF and COFA events. Error
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In the DS3 transmit direction, the TEMUX 84 inserts DS3 framing, X and P bits. When enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication Signals, Far End Receive Failure and idle signal can be inserted using either internal registers or can be configured for automatic insertion upon received errors. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of the first M sub-frame) is forced to toggle so that downstream equipment will not confuse an M23-formatted stream with stuck-at-1 C-bits for C-bit Parity application. Transmit timing is from an external reference or from the receive direction clock.
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be polled once per second, and are sized so as not to saturate at a 10-3 bit error rate. Transfer of count values to holding registers is initiated through the microprocessor interface.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
36
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The TEMUX 84 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.
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A SONET/SDH mapper maps and demaps up to 84 T1s, 63 E1s or three DS3s into three STS-1 SPEs, TUG3s or VC3s through three elastic stores. The fixed stuff (R) bits are all set to zeros or ones under microprocessor control. The bit asynchronous demapper performs majority vote C-bit decoding to detect stuff requests for T1, E1 and DS3 asynchronous mappings. The VT1.5/VT2/TU11/TU-12 mapper uses an elastic store and a jitter attenuator capability to minimize jitter introduced via bit stuffing.
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The SONET/SDH line side interface provides STS-1 SPE synchronous payload envelope processing and generation, TUG3 tributary unit group processing and generation within a VC4 virtual container and VC3 virtual container processing and generation. The payload processor aligns and monitors the performance of SONET virtual tributaries (VTs) or SDH tributary units (TUs). Maintenance functions per tributary include detection of loss of pointer, AIS alarm, tributary path signal label mismatch and tributary path signal label unstable alarms. Optionally interrupts can be generated due to the assertion and removal of any of the above alarms. Counts are accumulated for tributary path BIP-2 errors on a block or bit basis and for FEBE indications. The synchronous payload envelope generator generates all tributary pointers and calculates and inserts tributary path BIP-2. The generator also inserts FEBE, RDI and RFI in the V5 byte. Software can force AIS insertion on a per tributary basis.
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When configured as a DS3 or E3 framer the unchannelized payload of the DS3 and E3 links are available to an external device.
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Each of the seven 6312 kbit/s multiplexers per DS3 may be independently configured to multiplex and demultiplex four 1544 kbit/s DS1s or three 2048 kbit/s according to ITU-T Rec. G.747 into and out of a DS2 formatted signal. Tributary frequency deviations are accommodated using internal FIFOs and bit stuffing. The C-bits are set appropriately, with the option of inserting DS1 loopback requests. Interrupts can be generated upon detection of loopback requests in the received DS2. AIS may be inserted in any of the low speed tributaries in both multiplex and demultiplex directions.
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events (FERF, MERR, FERR, PERR, RAI, framing word errors) are still indicated while the DS2 framer is indicating OOF, based on the previous alignment.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
37
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
F G H J K L
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VSS VSS VSS VSS VSS VSS
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324 PBGA
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Bottom View
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22 21 20 19 18 17 16 15 14 13 12 11 10
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Figure 11
- Pin Diagram
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The TEMUX 84 is packaged in a 324-pin PBGA package having a body size of 23mm by 23mm and a ball pitch of 1.0 mm. The center 36 balls are not used as signal I/Os and are thermal balls. Pin names and locations are defined in the Pin Description Table in section 8. Mechanical information for this package is in the section 19.
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PIN DIAGRAM
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1 9 8 7 6 5 4 3 2 1
38
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
DS3 and E3 Line Side Interface RCLK[3] RCLK[2] RCLK[1] Input P1 T1 Y1
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RNEG/RLCV[3] RNEG/RLCV[2] RNEG/RLCV[1]
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RPOS[3:1] and RDAT[3:1] are sampled on the rising edge of the associated RCLK by default and may be enabled to be sampled on the falling edge of the associated RCLK by setting the RFALL bit in the DS3/E3 Master Receive Line Options register. Negative Input Pulse (RNEG[3:1]). RNEG[3:1] represent the negative pulses received on the B3ZSencoded DS3s or HDB3-encoded E3s when dual rail input format is selected. Line code violation (RLCV[3:1]). RLCV[3:1] represent receive line code violations when single rail input format is selected. RNEG[3:1] and RLCV[3:1] are sampled on the rising edge of the associated RCLK by default and may be enabled to be sampled on the falling edge of RCLK by setting the RFALL bit in the DS3/E3 Master Receive Line Options register.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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P3 T3 W2
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Receive Data Input (RDAT[3:1]). RDAT[3:1] represent the NRZ (unipolar) DS3 or E3 input data streams when single rail input format is selected.
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RPOS/RDAT[3] RPOS/RDAT[2] RPOS/RDAT[1]
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Input
P2 U1 V3
Positive Input Pulse (RPOS[3:1]). RPOS[3:1] represent the positive pulses received on the B3ZSencoded DS3s or HDB3-encoded E3s when dual rail input format is selected.
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Receive Input Clocks (RCLK[3:1]). RCLK[3:1] provide the receive direction timing for the three DS3s or E3s. RCLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clock inputs. The RCLK input frequency must always remain within +/-20 ppm such that the generated demultiplexed DS1 AIS frequency remains within +/- 32 ppm in channelized DS3 applications.
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Pin Name
Type
Pin Function No.
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PIN DESCRIPTION
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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TPOS[3:1] and TDAT[3:1] are updated on the falling edge of the associated TCLK by default but may be enabled to be updated on the rising edge of the associated TCLK by setting the TRISE bit in the DS3/E3 Master Transmit Line Options register. TPOS[3:1] and TDAT[3:1] are updated on TICLK[3:1] rather than TCLK[3:1] when the TICLK bit in the DS3/E3 Master Transmit Line Options register is set.
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Transmit Data Output (TDAT[3:1]). TDAT[3:1] represent the NRZ (unipolar) DS3 output data streams when single rail output format is selected.
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TPOS/TDAT[3] TPOS/TDAT[2] TPOS/TDAT[1]
Output R2 Transmit Positive Pulse (TPOS[3:1]). TPOS[3:1] U2 represent the positive pulses transmitted on the B3ZSAA1 encoded DS3 or HDB3-encoded E3 lines when dualrail output format is selected.
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TCLK[3] TCLK[2] TCLK[1]
Output R3 V1 W3
Transmit Clock (TCLK[3:1]). TCLK[3:1] provide timing for circuitry downstream of the DS3 and E3 transmitters of the TEMUX 84. TCLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clocks.
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Pin Name
Type
Pin Function No.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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TICLK[3] TICLK[2] TICLK[1]
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Input
T4 V4 Y2
Transmit input clock (TICLK[3:1]). TICLK[3:1] provides the transmit direction timing for the three DS3s or E3s. TICLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clocks.
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TNEG[3:1] and TMFP[3:1] are updated on the falling edge of the associated TCLK by default but may be enabled to be updated on the rising edge of the associated TCLK by setting the TRISE bit in the DS3/E3 Master Transmit Line Options register. TNEG[3:1] and TMFP[3:1] are updated on TICLK[3:1] rather than TCLK[3:1] when the TICLK bit in the DS3/E3 Master Transmit Line Options register is set.
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Transmit Multiframe Pulse (TMFP[3:1]). These signals mark the transmit frame alignment when configured for single rail operation. TMFP[3:1] indicate the position of overhead bits in the transmit transmission system stream, TDAT[3:1]. TMFP[3:1] are high during the first bit (X1) of the multiframe or E3 frame.
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TNEG/TMFP[3] TNEG/TMFP[2] TNEG/TMFP[1]
Output U4 Transmit Negative Pulse (TNEG[3:1]). TNEG[3:1] W1 represent the negative pulses transmitted on the AB1 B3ZS-encoded DS3 or HDB3-encoded E3 lines when dual-rail output format is selected.
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Pin Name
Type
Pin Function No.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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RDATO[3] RDATO[2] RDATO[1]
Output H2 K4 N2
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The demapped DS3 RSCLK must be externally dejittered when connecting to the PM73122 AAL1gator32 device. RSCLK[3:1] are the recovered clocks and timing references for RDATO[3:1], RFPO/RMFPO[3:1], and ROVRHD[3:1]. Framer Receive Data (RDATO[3:1]). RDATO[3:1] are valid when the TEMUX 84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. RDATO[3:1] are the received data aligned to RFPO/RMFPO[3:1] and ROVRHD[3:1]. RDATO[3:1] are updated on either the falling or rising edge of the associated RGAPCLK or RSCLK, depending on the value of the RSCLKR bit in the DS3 and E3 Master Unchannelized Interface Options register. By default, RDATO[3:1] will be updated on the falling edge of the associated RGAPCLK[3:1] or RSCLK[3:1].
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Framer Recovered Clock (RSCLK[3:1]). RSCLK[3:1] are valid when the TEMUX 84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. When a DS3 is demapped from SONET/SDH (i.e. LINEOPT_SPEx = 01), RSCLK is a gapped version of CLK52M.
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RGAPCLK[x] is the recovered clock and timing reference for RDATO[x]. RGAPCLK[3:1] are held either high or low during bit positions which correspond to overhead.
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RGAPCLK/RSCLK Output H4 [3] RGAPCLK/RSCLK L3 [2] RGAPCLK/RSCLK N3 [1]
Framer Recovered Gapped Clock (RGAPCLK[3:1]). RGAPCLK[3:1] are valid when the TEMUX 84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers and the RXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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ROVRHD[3] ROVRHD[2] ROVRHD[1]
Output H3 K1 N1
Framer Receive Overhead (ROVRHD[3:1]). ROVRHD[3:1] are valid when the TEMUX 84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers.
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ROVRHD[3:1] will be high whenever the data on RDATO[3:1] corresponds to an overhead bit position. ROVRHD[3:1] is updated on the either the falling or rising edge of the associated RSCLK depending on the setting of the RSCLKR bit in the DS3 and E3 Master Unchannelized Interface Options register.
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RFPO/RMFPO[3:1] are updated on either the falling or rising edge of the associated RSCLK depending on the setting of the RSCLKR bit in the DS3 and E3 Master Unchannelized Interface Options register.
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RMFPO[3:1] are aligned to RDATO[3:1] and indicate the position of the first bit in each DS3 M-frame and the first bit in each G.751 or G.832 E3 frame. This is selected by setting the RXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options Registers.
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RFPO[3:1] are aligned to RDATO[3:1] and indicate the position of the first bit in each DS3 M-subframe and the first bit in each G.751 E3 or G.832 E3 frame.
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RFPO/RMFPO[3] RFPO/RMFPO[2] RFPO/RMFPO[1]
Output H1 K2 M2
Framer Receive Frame Pulse/Multi-frame Pulse (RFPO/RMFPO[3:1]). RFPO/RMFPO[3:1] are valid when the TEMUX 84 is configured to be in framer only mode by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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TFPO/TMFPO[3:1] will be updated on the falling edge of TICLK when the associated TDATIFALL register bit is a logic 0 and on the rising edge when TDATIFALL is a logic 1. Framer Gapped Transmit Clock (TGAPCLK[3:1]). TGAPCLK[3:1] are valid when the TEMUX 84 is configured as DS3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers and setting the TXGAPEN bit to 1 in the DS3 and E3 Master Unchannelized Interface Options register. TGAPCLK[3:1] are derived from the transmit reference clocks TICLK[3:1] or from the receive clock if looptimed. The overhead bit (gapped) positions are generated internal to the device. TGAPCLK[3:1] are held high during the overhead bit positions. This clock is useful for interfacing to devices which source payload data only.
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In DS3 mode, TMFPO[3:1] pulse high for 1 out of every 4760 clock cycles, giving a reference M-frame indication. TMFPO[3:1] behaves the same as TFPO[3:1] for E3 applications. This is selected by setting the TXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options Registers.
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da
y,
14
In DS3 mode, TFPO[3:1] pulse high for 1 out of every 85 clock cycles, giving a reference M-subframe indication. In E3 mode, TFPO[3:1] pulse high to mark the first bit of the frame.
Se
pt
em
be
TFPO/TMFPO/ TGAPCLK[3] TFPO/TMFPO/ TGAPCLK[2] TFPO/TMFPO/ TGAPCLK[1]
r,
M3
20
04
J4
07
Output F4
Framer Transmit Frame Pulse/Multi-frame Pulse Reference (TFPO/TMFPO[3:1]). TFPO/TMFPO[3:1] are valid when the TEMUX 84 is configured as DS3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers and setting the TXGAPEN bit to 0 in the DS3 and E3 Master Unchannelized Interface Options register.
:4
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
TDATI[3] TDATI[2] TDATI[1]
es
da
Input
G2 J3 L2
Framer Transmit Data (TDATI[3:1]). TDATI[3:1] contain the serial data to be transmitted when the TEMUX 84 is configured as DS3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. TDATI[3:1] are sampled on the rising edge of the associated TICLK if the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0. If TXGAPEN is logic 1, then TDATI[3:1] are sampled on the rising edge of TGAPCLK. TDATI[3:1] can be configured to be sampled on the falling edge of the associated TICLK or TGAPCLK by setting the TDATIFALL bit in the DS3 and E3 Master Unchannelized Interface Options register.
y,
TGAPCLK[3:1] are used to sample the associated TDATI[3:1] inputs.
14
Se
In DS3 mode, TGAPCLK is gapped for one bit every 85 TICLK cycles. In E3 G.832 mode, TGAPCLK is gapped for the first two bytes of the frame. In E3 G.751 mode, TGAPCLK is gapped during the frame alignment signal, remote alarm indication bit, the national use bit, the justification service bits (bits 1 to 4 of Sets II, III and IV), and optionally during the bits available for justification (bits 5 to 8 of Set IV) as determined by the PYLD&JUST bit of the E3 Data Link Control register.
pt
em
be
r,
20
04
07
:4
3:
45
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
H-MVIP System Side Interfaces
nt Te a
m
of P
CMV8MCLK
Input
ar
tm
T22 Common 8M H-MVIP Clock (CMV8MCLK). The common 8.192 Mbit/s H-MVIP data provides the data clock for receive and transmit links configured for operation in 8.192 Mbit/s H-MVIP mode. CMV8MCLK is used to sample data on MVID[1:21], MVED[1:21], CASID[1:21], CASED[1:21], CCSID[1:3], CCSED[1:3] and TS0ID. CMV8MCLK is nominally a 50% duty cycle clock with a frequency of 16.384 MHz. The H-MVIP interfaces are enabled via the SYSOPT[1:0] bits in the Global Configuration register. If the TEMUX 84 is not configured for H-MVIP operation, this clock may be tied high or low.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
in
TFPI/TMFPI[3:1] are sampled on the rising edge of the associated TICLK. TFPI/TMFPI[3:1] can be configured to be sampled on the falling edge of the associated TICLK by setting the TDATIFALL bit to 1 in the Register 0x0202 + 0x100*N: DS3 and E3 Master Unchannelized Interface Options.
er
In
co
n
Tu
TMFPI[3:1] indicate the position of the first bit in each 4760-bit DS3 M-frame or the first bit in each E3 frame. TMFPI[3:1] are not required to pulse at every multiframe boundary. This is selected by setting the TXMFPI bit in the DS3 and E3 Master Unchannelized Interface Options Registers.
es
da
y,
14
Se
TFPI[3:1] indicate the position of all overhead bits in each DS3 M-subframe or the first bit in each G.751 E3 or G.832 E3 frame. TFPI[3:1] are not required to pulse at every overhead bit.
pt
em
be
r,
20
04
TFPI/TMFPI[3] TFPI/TMFPI[2] TFPI/TMFPI[1]
07
Input
G1 J1 M1
Framer Transmit Frame Pulse/Multiframe Pulse (TFPI/TMFPI[3:1]). TFPI/TMFPI[3:1] are valid when the TEMUX 84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers.
:4
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46
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
nt Te a
If the CMMFP bit of the Master H-MVIP Interface Configuration register is a logic 1, the CMVFPB is becomes a multiframe pulse. Mulitframe alignment is only relevant when the T1 F-bit or the E1 TS0 is being carried transparently in the egress direction and alignment to CAS signaling is required. To support any combination of SF, SLC96, ESF and E1, the CMVFPB must pulse low at a multiple of 48 frames at the beginning of the frame. The H-MVIP interfaces are enabled via the SYSOPT[1:0] bits in the Global Configuration register. If the TEMUX 84 is not configured for H-MVIP operation, this frame pulse may be tied high or low. The CMVFPB frame pulse occurs at multiples of 125us and is sampled on the falling edge of CMVFPC.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
m
of P
ar
tm
in
er
In
co
n
Tu
CMVFPB
Input
R22 Common H-MVIP Frame Pulse (CMVFPB). The active low common frame pulse for 8.192 Mbit/s HMVIP signals references the beginning of each frame for links operating in 8.192 Mbit/s H-MVIP mode.
es
The H-MVIP interfaces are enabled via the SYSOPT[1:0] bits in the Global Configuration registers. If the TEMUX 84 is not configured for H-MVIP operation, this clock may be tied high or low.
da
y,
14
Se
CMVFPC is used to sample CMVFPB. CMVFPC is nominally a 50% duty cycle clock with a frequency of 4.096 MHz. The falling edge of CMVFPC must be aligned with the falling edge of CMV8MCLK with no more than 10ns skew.
pt
em
be
r,
20
04
07
CMVFPC
Input
R20 Common H-MVIP Frame Pulse Clock (CMVFPC). The common 8.192 Mbit/s H-MVIP frame pulse clock provides the frame pulse clock for receive and transmit links configured for operation in 8.192 Mbit/s H-MVIP mode.
:4
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47
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
MVID[1] MVID[2] MVID[3] MVID[4] MVID[5] MVID[6] MVID[7] MVID[8] MVID[9] MVID[10] MVID[11] MVID[12] MVID[13] MVID[14] MVID[15] MVID[16] MVID[17] MVID[18] MVID[19] MVID[20] MVID[21]
Output B3 A3 A2 C5 A4 B5 C6 A5 B6 C7 D6 A6 A7 C8 B8 A8 D7 C9 B9 A9 D9
In
co
T1 and E1 links may be mixed on a TUG-3/DS3 granularity. Each of MVID[1:7], MVID[8:14] and MVID[15:21] carries 28 T1s or 21 E1s independent of the other two groups of seven. For E1 mode, MVID[7], MVID[14] and MVID[21] are unused.
n
Tu
es
da
MVID[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVID[x] is updated on every second rising or falling edge of the common H-MVIP 16.384Mb /s clock, CMV8MCLK, as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master and H-MVIP Interface Configuration register.
y,
14
Se
pt
em
be
r,
20
H-MVIP Ingress Data (MVID[1:21]). MVID[x] carries the recovered T1 or E1 channels which have passed through the elastic store. Each MVID[x] signal carries the channels of four complete T1s or E1s.
04
07
:4
3:
48
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
m
of P
ar
CCSID[1] CCSID[2] CCSID[3]
Output C16 Common Channel Signaling Ingress Data D18 (CCSID[1:3]). In T1 mode, CCSID[1] carries the 84 B17 common channel signaling channels extracted from each of the 84 T1s. In E1 mode, CCSID[1:3] carries up to 3 timeslots (15,16, 31) from each of the 63 E1s. CCSID is formatted according to the H-MVIP standard.
tm
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
in
er
CASID[1] CASID[2] CASID[3] CASID[4] CASID[5] CASID[6] CASID[7] CASID[8] CASID[9] CASID[10] CASID[11] CASID[12] CASID[13] CASID[14] CASID[15] CASID[16] CASID[17] CASID[18] CASID[19] CASID[20] CASID[21]
Output B18 A19 A20 B19 B20 A21 B21 D20 B22 C21 D21 E20 E21 C20 E22 F21 E19 G20 F22 G21 G22
CCSID[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSID is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master H-MVIP Interface Configuration register.
In
co
T1 and E1 links may be mixed on a TUG-3/DS3 granularity. Each of CASID[1:7], CASID[8:14] and CASID[15:21] carries 28 T1s or 21 E1s independent of the other two groups of seven. For E1 mode, CASID[7], CASID[14] and CASID[21] are unused.
n
Tu
es
da
CASID[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASID[x] is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master H-MVIP Interface Configuration register.
y,
14
Se
pt
em
be
r,
Channel Associated Signaling Ingress Data (CASID[1:21]). Each CASID[x] signal carries CAS for four complete T1s or E1s. CASID[x] carries the corresponding CAS values of the channel carried in MVID[x]. It also carries the framer and alarm statuses.
20
04
07
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49
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
MVED[1] MVED[2] MVED[3] MVED[4] MVED[5] MVED[6] MVED[7] MVED[8] MVED[9] MVED[10] MVED[11] MVED[12] MVED[13] MVED[14] MVED[15] MVED[16] MVED[17] MVED[18] MVED[19] MVED[20] MVED[21]
Input
B10 A10 D10 B11 A11 D12 B12 C12 D13 B13 C13 D14 A14 B14 C14 A15 B15 A16 C15 B16 A17
of P
MVED[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVID[x] is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. MVED[3] is a Schmitt triggered input. T1 and E1 links may be mixed on a TUG-3/DS3 granularity. Each of MVED[1:7], MVED[8:14] and MVED[15:21] carries 28 T1s or 21 E1s independent of the other two groups of seven. For E1 mode, MVED[7], MVED[14] and MVED[21] are unused.
nt Te a
m
ar
tm
in
er
In
co
n
Tu
H-MVIP Egress Data (MVED[1:21]). The egress data streams to be transmitted are input on these pins. Each MVED[x] signal carries the channels of four complete T1s or E1s formatted according to the HMVIP standard.
es
da
y,
14
Se
TS0ID is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. TS0ID is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master H-MVIP Interface Configuration register.
pt
em
be
r,
20
04
07
TS0ID
Output D17 E1 Timeslot 0 Ingress Data (TS0ID). In E1 mode, TS0ID carries the first timeslot of each frame.
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
nt Te a
m
of P
ar
CCSED[1], CCSED[2], CCSED[3]
tm
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
in
Input
H20 Common Channel Signaling Egress Data H21 (CCSED[1:3]). In T1 mode CCSED[1] carries the H22 common channel signaling channels to be transmitted in each of the T1s. In E1 mode CCSED carries up to 3 timeslots (15,16, 31) to be transmitted in each of the E1s. CCSED is formatted according to the H-MVIP standard. CCSED is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSED is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master H-MVIP Interface Configuration register.
er
CASED[1] CASED[2] CASED[3] CASED[4] CASED[5] CASED[6] CASED[7] CASED[8] CASED[9] CASED[10] CASED[11] CASED[12] CASED[13] CASED[14] CASED[15] CASED[16] CASED[17] CASED[18] CASED[19] CASED[20] CASED[21]
T1 and E1 links may be mixed on a TUG-3/DS3 granularity. Each of CASED[1:7], MVED[8:14] and CASED[15:21] carries 28 T1s or 21 E1s independent of the other two groups of seven. For E1 mode, CASED[7], CASED[14] and CASED[21] are unused.
In
co
n
Tu
es
CASED[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASED[x] is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master H-MVIP Interface Configuration register.
da
y,
14
Se
pt
em
be
r,
20
04
07
Input
H19 J20 J21 J22 J19 K20 K22 K19 L20 L22 M22 M21 M20 N19 N22 N20 P19 P22 P21 P20 R19
Channel Associated Signaling Egress Data (CASED[1:21]). Each CASED[x] signal carries CAS for four complete T1s or E1s formatted according to the H-MVIP standard. CASED[x] carries the corresponding CAS values of the channel data carried in MVED[x]. CASED[x] may also present inband information for the control of signaling insertion.
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
nt Te a
m
of P
ar
tm
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
in
er
IFBWDAT[3] IFBWDAT[2] IFBWDAT[1]
IFBWDAT[3:1] are sampled on the rising edge of the associated IFBWCLK input.
In
co
Input
N20 The Ingress Flexible Bandwidth Data L20 (IFBWDAT[3:1]). These inputs present bit serial data J20 for insertion into the System Drop Bus (SDDATA[7:0]). Only bits for which the associated IFBWEN input is sampled high are accepted. Each data input is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers. The bit ordering is big-endian, i.e. data presented on SDDATA[7] is received earlier in time than data presented in the same byte on SDDATA[0].
n
Each IFBWCLK samples the associated IFBWDAT[3:1] and IFBWEN[3:1] inputs on the rising edge.
Tu
es
IFBWCLK[3:1] may have a maximum frequency of 51.84 MHz and may be gapped if required.
da
y,
14
Se
pt
em
IFBWCLK[3] IFBWCLK[2] IFBWCLK[1]
be
r,
Input
N22 The Ingress Flexible Bandwidth Clocks K19 (IFBWCLK[3:1]). The IFBWCLK[3:1] clocks provide H19 the timing for an arbitrary bandwidth payload to be inserted into the System Drop Bus (SDDATA[7:0]). Each clock is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers.
20
Port #1 is associated with SBI SPE #1. Port #2 is associated with SBI SPE #2. Port #3 is associated with SBI SPE #3.
04
07
Flexible Bandwidth Ports
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ed
by
Co
nt e
nt Te a
m
of P
EFBWDREQ[3] EFBWDREQ[2] EFBWDREQ[1]
ar
Input
tm
Each EFBWCLK samples the associated EBWDREQ on the rising edge and updates the associated EFBWDAT] and EFBWEN on the falling edge.
P21 The Egress Flexible Bandwidth Data Requests M21 (EFBWREQ[3:1]). The data request input must be J19 asserted high for a EFBWCLK cycle for each bit of data required. In response to sampling EFWBDREQ[3:1] high, the associated EFBWDAT output will either present an available bit a cycle later with an accompanying assertion of the associated EFBWEN or ignore the request if no data is ready. In many applications (eg. frame relay and ATM), every request will be acknowledged with data. In applications where the source data is fixed, it is permissible to hold EFBWDREQ[3:1] high, in which case EFBWEN identifies valid bytes. EFBWDREQ[3:1] are sampled on the rising edge of the associated EFBWCLK input.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
in
er
In
co
EFBWCLK[3:1] may have a maximum frequency of 51.84 MHz and may be gapped if required.
n
Tu
es
da
y,
14
EFBWCLK[3] EFBWCLK[2] EFBWCLK[1]
Se
Input
P22 The Egress Flexible Bandwidth Clocks M22 (EFBWCLK[3:1]). The EFBWCLK[3:1] clocks provide J22 the timing for an arbitrary bandwidth payload extracted from the System Add Bus (SADATA[7:0]). Each clock is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers.
pt
IFBWEN[3:1] are sampled on the rising edge of the associated IFBWCLK input.
em
be
r,
20
04
IFBWEN[3] IFBWEN[2] IFBWEN[1]
07
Input
P19 The Ingress Flexible Bandwidth Enables L22 (IFBWEN[3:1]). A logic high on any of these inputs J21 indicates a valid bit on the associated IFBWDAT input. The IFBWEN[3:1] inputs are constrained such that the maximum data rate of each of IFBWDAT[3:1] is less than 48.96 Mbit/s.
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Recovered T1 and E1 Clocks
RECVCLK2
nt Te a
m
RECVCLK1
Output F2
of P
ar
tm
Output E4
RECVCLK3
Co
nt e
Output G3
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
in
er
EFBWEN[3:1] are updated on the falling edge of the associated EFBWCLK input. Recovered Clock 1 (RECVCLK1). This clock output is a recovered and de-jittered clock from any one of the 84 T1 framers or 63 E1 framers. Recovered Clock 2 (RECVCLK2). This clock output is a recovered and de-jittered clock from any one of the 84 T1 framers or 63 E1 framers. Recovered Clock 3 (RECVCLK3). This clock output is a recovered and de-jittered clock from any one of the 84 T1 framers or 63 E1 framers.
In
co
EFBWEN[3] EFBWEN[2] EFBWEN[1]
Output E22 The Egress Flexible Bandwidth Enables D20 (EFBWEN[3:1]). A logic high on any of these outputs B18 indicates a valid bit on the associated EFBWDAT output. The EFBWEN[3:1] will only be asserted, with a one cycle latency, in response to a sampled logic high on the associated EFBWDREQ, and then only if data is available for presenting on the associated EFBWDAT.
n
Tu
es
da
EFBWDAT[3:1] are updated on the falling edge of the associated EFBWCLK input.
y,
14
Se
pt
em
be
r,
20
04
EFBWDAT[3] EFBWDAT[2] EFBWDAT[1]
Output F21 The Egress Flexible Bandwidth Data B22 (EFBWDAT[3:1]). These outputs present bit serial A19 data extracted from the System Add Bus (SADATA[7:0]). Only bits for which the associated EFBWEN output is simultaneously high are valid. Each data input is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers. The bit ordering is big-endian, i.e. data received on SADATA[7] is transmitted earlier in time than data received in the same byte on SADATA[0].
07
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
nt Te a
m
of P
ar
tm
nt e
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
in
er
LREFCLK
Input
Y4
Line Reference Clock (LREFCLK). This signal provides reference timing for the SONET telecom bus interface. On the incoming byte interface of the telecom bus, LDC1J1V1, LDDATA[7:0], LDDP, LDPL, LDTPL, LDV5, LDAIS and LAC1 are sampled on the rising edge or LREFCLK. In the outgoing byte interface, LADATA[7:0], LADP, LAPL, LAC1J1V1 and LAOE/LATPL are updated on the rising edge of LREFCLK. This clock may be held low if the Telecom Bus interface is unused. This clock is nominally a 19.44 MHz +/-20ppm or 77.76 MHz +/-20ppm clock with a 50% duty cycle. This clock must be phase locked to SREFCLK and can be external connected to SREFCLK.
In
Telecom Line Side Interface
co
This input may be tied to ground in applications that do not use the RECVCLK1/2/3 outputs as 2.048 MHz clocks.
n
Tu
es
da
y,
14
Se
XCLK_E1
Input
F3
E1 Crystal Clock Input (XCLK_E1). This input clocks the digital phase locked loop that performs jitter attenuation on the E1 recovered clocks which drive the RECVCLK1/2/3 outputs. XCLK_E1 is nominally a 49.152 MHz 32ppm, 50% duty cycle clock when configured for E1 modes.
pt
This input may be tied to ground in applications that do not use the RECVCLK1/2/3 outputs as s1.544 MHz clocks.
em
be
r,
20
04
07
XCLK_T1
Input
E2
T1 Crystal Clock Input (XCLK_T1). This input clocks the digital phase locked loop that performs jitter attenuation on the T1 recovered clocks which drive the RECVCLK1/2/3 outputs. XCLK_T1 is nominally a 37.056 MHz 32ppm, 50% duty cycle clock.
:4
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LAC1 is sampled on the rising edge of LREFCLK.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In
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es
LAC1 is set high to mark the first C1 byte of the first transport envelope frame of the 4 frame multiframe on the LADATA[7:0] bus. LAC1 need not be presented on every occurrence of the multiframe.
da
y,
14
Se
pt
LAC1
Input
W10 Line Add C1 Frame Pulse (LAC1). The Add bus timing signal identifies the frame and multiframe boundaries on the Add Data bus LADATA[7:0].
em
L77 is expected to be held static.
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L77
Input
AA4 The Line 77.76 MHz select input determines the expected frequency of LREFCLK. If L77 is low, LREFCLK is expected to be 19.44 MHz. If L77 is high, LREFCLK is expected to be 77.76 MHz and data is driven and sampled every fourth cycle. L77 is a Schmitt triggered input.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tm
When L77 high, LAC1J1V1 is only valid (i.e. identifies the first C1, J1 and V1 of the concatenated STM-4 data stream) if the LSTM[1:0] bits in the Master Bus Configuration register (0x0006) are set to "00". LAC1J1V1 is updated on the rising edge of LREFCLK.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In a system with multiple TEMUX 84s sharing the same Line Add bus only one device should have LAC1J1V1 connected. All devices must be configured via the TXPTR[9:0] bits in the SONET/SDH Transmit Pointer Configuration and TTMP Telecom Interface Configuration registers for the same J1 location.
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LAC1J1V1
Output AA11 Line Add Bus Composite Timing Signal (LAC1J1V1). The Add bus composite timing signal identifies the frame, payload and tributary multiframe boundaries on the Line Add Data bus LADATA[7:0]. LAC1J1V1 pulses high with the Line Add Payload Active signal LAPL set low to mark the first STS-1 (STM-0/AU3) identification byte or equivalently the STM identification byte C1. Optionally the LAC1J1V1 signal pulses high with LAPL set high to mark the path trace byte J1. Optionally the LAC1J1V1 signal pulses high on the V1 byte to indicate tributary multiframe boundaries.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
nt Te a
Line Add Bus Tributary Payload Active (LATPL). The tributary payload active signal marks the bytes carrying the tributary payload. LATPL is high during each tributary payload byte on the LADATA[7:0] bus. LATPL will be low during transport overhead, path overhead, V1 bytes and V2 bytes. To indicate pointer adjustments, LATPL will be asserted appropriately during the V3 byte and following byte for the tributary. By default, LATPL is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers and during the J1 and V1 byte positions. As options, LATPL can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time. LAOE/LATPL is updated on the rising edge of LREFCLK.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In
This pin is intended to control an external multiplexer when multiple TEMUX 84s are driving the Telecom Add bus during their individual tributaries. This same function is accomplished with the Add bus tristate drivers but increased tolerance to tributary configuration problems is possible with an external mux. This output is controlled via the LAOE bit in the TTMP Tributary Control registers when the egress VTPP is bypassed. When the egress VTPP is not bypassed or a TU-3 is being mapped, LAOE is high.
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Line Add Bus Output Enable (LAOE). The Add Bus output enable signal is asserted high whenever the Line Add Bus is being driven which is co-coincident with the Line Add bus outputs coming out of tri-state.
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LAOE/LATPL
Tristate AB11 The LATPLSEL bit of the SONET/SDH Master Egress Output VTPP Configuration register determines the function of this tristate output. When LATPLSEL is logic 1, the signal is LATPL. When LATPLSEL is logic 0, the signal is LAOE.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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LADATA[7:0] is updated on the rising edge of LREFCLK.
In
co
By default, LADATA[7:0] is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers and during the J1 (when LAJ1EN bit is logic 1) and V1 (when LAJ1EN bit is logic 1) byte positions; otherwise, it is high impedance. As options, LADATA[7:0] can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time.
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LADATA[0] LADATA[1] LADATA[2] LADATA[3] LADATA[4] LADATA[5] LADATA[6] LADATA[7]
Output W14 Line Add Bus Data (LADATA[7:0]). The add bus data Tristate Y13 contains the SONET transmit payload data in byte AA13 serial format. All transport overhead bytes are set to AB13 00h. The phase relation of the SPE (VC) to the W13 transport frame is determined by the Add Bus AA12 composite timing signal LAC1J1V1 and is software W12 programmable to any valid pointer offset. LADATA[7] is W11 the most significant bit (corresponding to bit 1 of each serial word, the first bit to be transmitted).
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
By default, LADP is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers and during the J1 (when LAJ1EN bit is logic 1) and V1 (when LAJ1EN bit is logic 1) byte positions; otherwise, it is high impedance. As options, LADP can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time.
m
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LAPL
Output AA14 Line Add Bus Payload Active (LAPL). The Add Bus payload active signal identifies the payload bytes on Tristate LADATA[7:0]. LAPL is set high during path overhead and payload bytes and low during transport overhead bytes. By default, LAPL is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers and during the J1 (when LAJ1EN bit is logic 1) and V1 (when LAJ1EN bit is logic 1) byte positions; otherwise, it is high impedance. As options, LAPL can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time. LAPL is updated on the rising edge of LREFCLK.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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LADP is updated on the rising edge of LREFCLK.
In
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LADP
Output AB14 Line Add Bus Data Parity (LADP). The Add Bus data parity signal carries the parity of the outgoing signals. Tristate The parity calculation encompasses the LADATA[7:0] bus and optionally the LAC1J1V1 and LAPL signals. LAC1J1V1 and LAPL can be included in the parity calculation by setting the INCLAC1J1V1 and INCLAPL register bits in the SONET/SDH Master Egress Configuration register high, respectively. Odd parity is selected by setting the LAOP register bit in the same register high and even parity is selected by setting the LAOP bit low.
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
by
Co
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LDDP
Input
ar
tm
LDDATA[0] LDDATA[1] LDDATA[2] LDDATA[3] LDDATA[4] LDDATA[5] LDDATA[6] LDDATA[7]
Y7
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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LDDATA[7:0] is sampled on the rising edge of LREFCLK.
Line Drop Bus Data Parity (LDDP). The incoming data parity signal carries the parity of the incoming signals. The parity calculation encompasses the LDDATA[7:0] bus and optionally the LDC1J1V1 and LDPL signals. LDC1J1V1 and LDPL can be included in the parity calculation by setting the INCLDC1J1V1 and INCLDPL bits in the SONET/SDH Master Ingress Configuration register high, respectively. Odd parity is selected by setting the LDOP bit in the Master SONET/SDH Ingress Configuration register high and even parity is selected by setting the LDOP bit low. LDDP is sampled on the rising edge of LREFCLK.
In
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Tu
Input
W5 AA6 AB5 Y3 Y6 AA5 AB4 AB3
Line Drop Bus Data (LDDATA[7:0]). The drop bus data contains the SONET/SDH receive payload data in byte serial format. LDDATA[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first.
es
LAV5 is updated on the rising edge of LREFCLK.
da
By default, LAV5 is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers and during the J1 (when LAJ1EN bit is logic 1) and V1 (when LAJ1EN bit is logic 1) byte positions; otherwise, it is high impedance. As options, LAV5 can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time.
y,
14
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LAV5
Output W15 Line Add Bus V5 Byte (LAV5). The outgoing tributary V5 byte signal marks the various tributary V5 bytes. Tristate LAV5 marks each tributary V5 byte on the LADATA[7:0] bus when high.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LDPL
Input
ar
LDPL is set high during path overhead and payload bytes and low during transport overhead bytes. LDPL is set high during the H3 byte to indicate a negative pointer justification and low during the byte following H3 to indicate a positive pointer justification event. LDPL is sampled on the rising edge of LREFCLK. Line Drop Bus V5 Byte (LDV5). The incoming tributary V5 byte signal marks the various tributary V5 bytes. LDV5 marks each tributary V5 byte on the LDDATA[7:0] bus when high. The LDV5 input is only used if the Ingress VTPP is bypassed (i.e. the IVTPPBYP bit of the SONET/SDH Master Ingress Configuration register is logic 1.) LDV5 is sampled on the rising edge of LREFCLK.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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LDV5
Input
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tm
W6
in
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In
co
AB7 Line Drop Bus Payload Active (LDPL). The payload active signal identifies the bytes on LDDATA[7:0] that carry payload bytes.
n
Tu
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LDC1J1V1 is sampled on the rising edge of LREFCLK.
da
Optionally LDC1J1V1 indicates multiframe alignment when high during the first V1 bytes of each envelope.
y,
14
LDC1J1V1 is set high while LDPL is low to mark the first C1 byte of the transport envelope frame on the LDDATA[7:0] bus. LDC1J1V1 is set high while LDPL is high to mark each J1 byte of the synchronous payload envelope(s) on the LDDATA[7:0] bus. LDC1J1V1 must be present at every occurrence of the first C1 and all J1 bytes.
Se
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LDC1J1V1
Input
AB6 Line Drop C1/J1 Frame Pulse (LDC1J1V1). The input C1/J1 frame pulse identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming SONET stream.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tm
RADEASTCK
Input
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W7
nt Te a
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Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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LDAIS is sampled on the rising edge of LREFCLK. Remote Alarm Port East Clock (RADEASTCK). The remote serial alarm port east clock provides timing for the east remote serial alarm port. It is nominally a 9.72 MHz clock, but can range from 1.344 MHz to 10 MHz. Inputs RADEASTFP and RADEAST are sampled on the rising edge of RADEASTCK.
In
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Tu
LDAIS
Input
AA8 Line Drop Bus Tributary Path Alarm Indication Signal (LDAIS). The active high tributary path alarm indication signal identifies tributaries on the incoming data stream LDDATA[7:0] that are in AIS state. When this signal is available, the internal pointer processor can be bypassed. LDAIS is invalid when LDTPL is low. LDAIS is only respected for asynchronously mapped tributaries.
es
LDTPL is sampled on the rising edge of LREFCLK.
da
LDTPL is high during each tributary payload byte on the LDDATA[7:0] bus. In floating mode, LDTPL contains valid data only for bytes in the VC3 or VC4 virtual containers, or the STS-1 SPE. It should be ignored for bytes in the transport overhead. In locked mode, LDTPL is low for transport overhead.
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LDTPL
Input
Y8
Line Drop Bus Tributary Payload Active (LDTPL). The tributary payload active signal marks the bytes carrying the tributary payload which have been identified by an external payload processor. When this signal is available, the internal pointer processor can be bypassed. LDTPL is only respected for asynchronously mapped tributaries.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tm
RADWESTCK
Input
of P
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W9
nt e
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Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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RADEAST is sampled on the rising edge of RADEASTCK. Remote Alarm Port West Clock (RADWESTCK). The remote serial alarm port west clock provides timing for the west remote serial alarm port. It is nominally a 9.72 MHz clock, but can range from 1.344 MHz to 10 MHz. Inputs RADWESTFP and RADWEST are sampled on the rising edge of RADWESTCK.
In
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RADEAST
Input
AA9 Remote Alarm Port Data East (RADEAST). The remote serial alarm port east carries the tributary path BIP-2 error count, RDI status, and RFI status in the east remote serial alarm port. The first BIP-2 error bit of tributary TU #1 in TUG2 #1 of TUG3 #1 on RADEAST is marked by a high level on RADEASTFP. The status carried on RADEAST is software selectable to be reported by the RDI, RFI and REI alarms and is selectable to be associated with any tributary on the outgoing data stream LADATA[7:0].
y,
RADEASTFP is sampled on the rising edge of RADEASTCK.
14
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07
RADEASTFP
Input
Y9
Remote Alarm Port East Frame Pulse (RADEASTFP). The remote serial alarm port east frame pulse is used to locate the alarm bits of the individual tributaries in the east remote serial alarm port. RADEASTFP is set high to mark the first BIP-2 error bit of tributary TU #1 in TUG2 #1 of TUG3 #1 carried in RADEAST. RADEASTFP must be set high to mark every occurrence of this bit. TEMUX 84 will not flywheel on RADEASTFP in order to accommodate a variety of RADEASTCK frequencies.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tm
CLK52M
Input
of P
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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AB10 52 MHz Clock Reference (CLK52M). This clock reference is used to generate a gapped DS3 clock when demapping a DS3 from the SONET stream and also to generate a gapped DS3/E3 clock when receiving a DS3/E3 from the SBI bus interface. This clock has two nominal values. The first is a nominal 51.84 MHz 50% duty cycle clock that must be used when an E3 is received on the SBI Add bus interface. The second is a nominal 44.928 MHz 50% duty cycle clock that must be used when demapping a DS3 from SONET. The expected frequency is determined by the FASTCLKFREQ bit of the SONET/SDH Master DS3 Clock Generation Control register.
in
er
RADWESTFP is sampled on the rising edge of RADWESTCK.
In
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Tu
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da
RADWEST
Input
AA10 Remote Alarm Port Data West (RADWEST). The remote serial alarm port west carries the tributary path BIP-2 error count, RDI status, and RFI status in the west remote serial alarm port. The first BIP-2 error bit of tributary TU #1 in TUG2 #1 of TUG3 #1 on RADWEST is marked by a high level on RADWESTFP. The status carried on RADWEST is software selectable to be reported by the RDI, RFI and REI alarms and is selectable to be associated with any tributary on the outgoing data stream LADATA[7:0].
y,
RADWESTFP is sampled on the rising edge of RADWESTCK.
14
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em
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07
RADWESTFP
Input
Y10 Remote Alarm Port West Frame Pulse (RADWESTFP). The remote serial alarm port west frame pulse is used to locate the alarm bits of the individual tributaries in the west remote serial alarm port. RADWESTFP is set high to mark the first BIP-2 error bit of tributary TU #1 in TUG2 #1 of TUG3 #1 carried in RADWEST. RADWESTFP must be set high to mark every occurrence of this bit. TEMUX 84 will not flywheel on RADWESTFP in order to accommodate a variety of RADWESTCK frequencies.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
of P
SREFCLK must be active for all applications, except DS3/E3 framer only mode when the system interface is serial clock and data. When the SYSOPT register bits are binary 01 (H-MVIP interface), SREFCLK is required to be 19.44 MHz. This clock must be phase locked to LREFCLK and can be external connected to LREFCLK. When passing transparent virtual tributaries between the telecom bus and the SBI bus, SREFCLK must be the same frequency as LREFCLK (i.e. S77 = L77). When operating in serial DS3 mode, the SREFCLK can be +/- 50 ppm.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In
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es
SREFCLK
Input
C10 System Reference Clock (SREFCLK). This system reference clock is a nominal 19.44 MHz +/-20ppm or 77.76 MHz +/-20ppm 50% duty cycle clock. This clock is common to both the add and drop sides of the SBI bus.
da
The TEMUX may be configured to ignore the CTCLK input and lock to the data or one of the recovered Ingress clocks instead, RECVCLK1, RECVCLK2 and RECVCLK3. The receive tributary clock is automatically substituted for CTCLK if line loopback or looptiming is enabled.
y,
14
Se
pt
em
be
r,
20
04
CTCLK
Input
F19 Common Transmit Clock (CTCLK). This input signal is used as a reference transmit tributary clock which can be used in egress Clock Master modes. CTCLK must be multiple of 8 kHz. The transmit clock is derived by the jitter attenuator PLL using CTCLK as a reference.
07
Scaleable Bandwidth Interconnect Interface
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
S77 is expected to be held static.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In
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14
Se
This signal is a don't care when the SYSOPT register bits are binary 01 (H-MVIP interface). In this mode, SREFCLK is required to be 19.44 MHz.
pt
em
be
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04
07
S77
Input
D10 The SBI 77.76 MHz select input determines the expected frequency of SREFCLK. If S77 is low, SREFCLK is expected to be 19.44 MHz. If S77 is high, SREFCLK is expected to be 77.76 MHz and data is driven and sampled every fourth cycle. S77 is a Schmitt triggered input.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
of P
ar
tm
nt Te a
m
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The TEMUX 84 can be configured to generate this frame pulse. Only one device on the SBI bus should generate this signal. By default this signal is not enabled to generate the frame pulse. If a SDC1FP pulse is received at an unexpected cycle, the Drop bus with become high-impedance until two consecutive valid SDC1FP pulses occur. The system frame pulse is a single SREFCLK cycle long and is updated on the rising edge of SREFCLK. This signal must be held low if the SBI and H-MVIP buses are both not being used.
In
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n
Tu
es
da
y,
14
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pt
em
be
r,
20
04
07
SDC1FP
I/O
B3
SBI Drop C1 Frame Pulse (SDC1FP). The SDC1FP C1 frame pulse synchronizes devices interfacing to the Insert SBI bus. The frame pulse indicates SBI bus multiframe alignment which occurs every 500 S, therefore this signal is pulsed every 9720 SREFCLK cycles (38880 cycles if S77 is high). This signal does not need to occur every SBI multiframe and is also used to indicate T1 and E1 multiframe alignment in synchronous SBI mode by pulsing at multiples of every 12 SBI multiframes (48 T1/E1 frames). In synchronous locked mode, as selected by the SYNCSBI context bit programmed through the RX-SBI-ELST Indirect Channel Data register, SDC1FP pulses every 116640 SREFCLK cycles (466560 cycles if S77 is high). If the SYNCSBI bit is logic 1 for at least one tributary, SDC1FP must indicate T1 and E1 multiframe alignment.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
of P
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tm
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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SADP
Input
A14 System Add Bus Data Parity (SADP). The system add bus signal carries the even or odd parity for the add bus signals SADATA[7:0], SAPL and SAV5. The TEMUX 84 monitors the add bus parity during all cycles when S77 is low and during the entire selected STM-1 when S77 is high. SADP is sampled on the rising edge of SREFCLK.
In
SADATA[0] SADATA[1] SADATA[2] SADATA[3] SADATA[4] SADATA[5] SADATA[6] SADATA[7]
SADATA[7:0] is sampled on the rising edge of SREFCLK.
co
n
Tu
es
da
y,
Input
A11 D12 B12 C12 D13 B13 C13 D14
System Add Bus Data (SADATA[7:0]). The System add data bus is a time division multiplexed bus which carries the E1, T1 and DS3 tributary data is byte serial format over the SBI bus structure. This device only monitors the add data bus during the timeslots assigned to this device.
14
This signal must be held low if the SBI bus is not being used.
Se
pt
em
be
r,
20
04
07
SAC1FP
Input
B11 SBI Add C1 Frame Pulse (SAC1FP). The Extract C1 frame pulse synchronizes devices interfacing to the Extract SBI bus. The frame pulse indicates SBI bus multiframe alignment which occurs every 500 S, therefore this signal is pulsed every 9720 SREFCLK cycles (38880 cycles if S77 is high). This signal does not need to occur every SBI multiframe. SAC1FP is sampled on the rising edge of SREFCLK.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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SAV5
Input
C14 System Add Bus Payload Indicator (SAV5). The add bus payload indicator locates the position of the floating payloads for each tributary within the SBI bus structure. Timing differences between the tributary timing and the synchronous SBI bus are indicated by adjustments of this payload indicator relative to the fixed SBI bus structure. All timing adjustments indicated by this signal must be accompanied by appropriate adjustments in the SAPL signal. The TEMUX 84 only monitors the add bus payload indicator signal during the tributary timeslots assigned to this device. SAV5 is sampled on the rising edge of SREFCLK.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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SAPL is sampled on the rising edge of SREFCLK.
In
The TEMUX 84 only monitors the add bus payload active signal during the tributary timeslots assigned to this device.
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In the flexible bandwidth configuration, SAPL may only be asserted in response to a logic high on the SAJUST_REQ. SAPL shall be high an equal or less number of cycles than SAJUST_REQ. (Some applications require an exact one-to-one correspondence.)
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07
SAPL
Input
B14 System Add Bus Payload Active (SAPL). The add bus payload active signal indicates valid data within the SBI bus structure. This signal must be high during all octets making up a tributary. This signal goes high during the V3 or H3 octet of a tributary to indicate negative timing adjustments between the tributary rate and the fixed SBI bus structure. This signal goes low during the octet after the V3 or H3 octet of a tributary to indicate positive timing adjustments between the tributary rate and the fixed SBI bus structure.
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Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tm
SAJUST_REQ has a different significance in the flexible bandwidth mode. In this mode, SAJUST_REQ is high for one SREFCLK cycle for each byte that can be accepted. A valid byte on SADATA[7:0] with an accompanying SAPL assertion is expected in response. The TEMUX 84 only drives the justification request signal during the tributary timeslots assigned to this device. When operating in 19.44 MHz mode (i.e. S77 low), SAJUST_REQ is aligned by the SAC1FP input. When operating in 77.76 MHz mode (i.e. S77 high), SAJUST_REQ's alignment is relative to the SDC1FP signal. SAJUST_REQ is updated on the rising edge of SREFCLK.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In
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Positive timing adjustments are requested by asserting justification request high during the octet following the V3 or H3 octet. The Link Layer device responds to this request by not sending an octet during the V3 or H3 octet of the next multi-frame.
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14
This active high signal indicates negative timing adjustments when asserted high during the V3 or H3 octet of the tributary. In response to this the Link Layer device sends an extra byte in the V3 or H3 octet of the next SBI bus multi-frame.
Se
pt
em
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04
Tristate
07
SAJUST_REQ
Output A2
System Add Bus Justification Request (SAJUST_REQ). The justification request signals the Link Layer device to speed up, slow down or maintain the rate which it is sending data to the TEMUX 84. This is only used when the TEMUX 84 is the timing master for the tributary transmit direction.
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
SDPL
Output A7 Tristate
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System Drop Bus Payload Active (SDPL). The payload active signal indicates valid data within the SBI bus structure. This signal is asserted during all octets making up a tributary. This signal goes high during the V3 or H3 octet of a tributary to accommodate negative timing adjustments between the tributary rate and the fixed SBI bus structure. This signal goes low during the octet after the V3 or H3 octet of a tributary to accommodate positive timing adjustments between the tributary rate and the fixed SBI bus structure. In the flexible bandwidth configuration, SDPL is asserted for each byte as it becomes available. Therefore, SDPL may be high or low arbitrarily during any SREFCLK cycle. The TEMUX 84 only drives the payload active signal during the tributary timeslots assigned to this device. SDPL is updated on the rising edge of SREFCLK.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In
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Tu
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SDDP is updated on the rising edge of SREFCLK.
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14
Tristate
Se
SDDP
Output A6
System Drop Bus Data Parity (SDDP). The system drop bus signal carries the even or odd parity for the drop bus signals SDDATA[7:0], SDPL and SDV5. Whenever the TEMUX 84 drives the data bus, the parity is valid.
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SDDATA[0] SDDATA[1] SDDATA[2] SDDATA[3] SDDATA[4] SDDATA[5] SDDATA[6] SDDATA[7]
Output C5 Tristate A4 B5 C6 A5 B6 C7 D6
SDDATA[7:0] is updated on the rising edge of SREFCLK.
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System Drop Bus Data (SDDATA[7:0]). The System drop data bus is a time division multiplexed bus which carries the E1, T1 and DS3 tributary data is byte serial format over the SBI bus structure. This device only drives the data bus during the timeslots assigned to this device.
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72
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
SDV5 is updated on the rising edge of SREFCLK.
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SBIDET[0] SBIDET[1]
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Input
tm
A15 SBI Bus Activity Detection (SBIDET[1:0]). The SBI B15 bus activity detect input detects tributary collisions between devices sharing the same SBI bus. Each SBI device driving the bus also drives an SBI active signal (SBIACT). This pair of activity detection inputs monitors the active signals from two other SBI devices. When unused this signal should be connected to ground. These inputs only have effect when the SBI bus is configured for 19.44MHz (i.e. S77 is low). A collision is detected when either of SBIDET[1:0] signals are active concurrently with this device driving SBIACT. When collisions occur the SBI drivers are disabled and an interrupt is generated to signal the collision.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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This output is updated on the rising edge or SREFCLK.
In
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SBIACT
Output A3
SBI Output Active (SBIACT). The SBI Output Active indicator is high whenever the TEMUX 84 is driving the SBI drop bus signals. This signal is used by other TEMUX 84s or other SBI devices to detect SBI configuration problems by detecting other devices driving the SBI bus during the same tributary as the device listening to this signal.
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The TEMUX 84 only drives the payload Indicator signal during the tributary timeslots assigned to this device.
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Se
All timing adjustments indicated by this signal are accompanied by appropriate adjustments in the SDPL signal.
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Tristate
07
SDV5
Output C8
System Drop Bus Payload Indicator (SDV5). The payload indicator locates the position of the floating payloads for each tributary within the SBI bus structure. Timing differences between the tributary timing and the synchronous SBI bus are indicated by adjustments of this payload indicator relative to the fixed SBI bus structure.
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
CSB
Input
The CSB input has an integral pull up resistor. RDB Input W17 Active Low Read Enable (RDB). This signal is low during TEMUX 84 register read accesses. The TEMUX 84 drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. AB16 Active Low Write Strobe (WRB). This signal is low during a TEMUX 84 register write access. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. U22 Bidirectional Data Bus (D[7:0]). This bus provides T20 TEMUX 84 register read and write accesses. V19 U21 U20 W22 Y22 Y21
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]
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I/O
In
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WRB
Input
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AA15 Active Low Chip Select (CSB). This signal is low during TEMUX 84 register accesses.
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04
INTB
Output T21 Active low Open-Drain Interrupt (INTB). This signal goes low when an unmasked interrupt event is OD detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source.
07
Microprocessor Interface
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
RSTB
Input
TCK
Input
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JTAG Interface
tm
B1
TMS
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Input
D2
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
TDI
Co
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Input
E3
in
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Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. Test Mode Select (TMS). This signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. Test Data Input (TDI). This signal carries test data into the TEMUX 84 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor.
In
co
ALE
Input
AA22 Address Latch Enable (ALE). This signal is active high and latches the address bus A[12:0] when low. When ALE is high, the internal address latches are transparent. It allows the TEMUX 84 to interface to a multiplexed address/data bus. The ALE input has an integral pull up resistor.
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Tu
W20 Active Low Reset (RSTB). This signal provides an asynchronous TEMUX 84 reset. RSTB is a Schmitt triggered input with an integral pull up resistor.
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A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12]
14
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Input
AB22 Address Bus (A[12:0]). This bus selects specific AA21 registers during TEMUX 84 register accesses. Y19 Signal A[12] selects between normal mode and test AA20 mode register access. A[12] has an integral pull down AA19 resistor. Tie A[12] directly to ground unless access to AB20 bit HIZIO in test register 0x1000 is required. AA18 W19 AB18 AA17 W18 Y16 AA16
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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Co
VDD3.3[19] VDD3.3[18] VDD3.3[17] VDD3.3[16] VDD3.3[15] VDD3.3[14] VDD3.3[13] VDD3.3[12] VDD3.3[11] VDD3.3[10] VDD3.3[9] VDD3.3[8] VDD3.3[7] VDD3.3[6] VDD3.3[5] VDD3.3[4] VDD3.3[3] VDD3.3[2] VDD3.3[1]
Power A18 Power (VDD3.3[19:1]). The VDD3.3[19:1] pins should A22 be connected to a well decoupled +3.3V DC power AB17 supply. D11 D16 D4 E1 F20 L1 L19 R21 R4 V2 W16 W4 W8 Y18 Y20 Y5
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In
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Power and Ground Pins
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Note that if not used, TRSTB must be connected to the RSTB input.
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14
Se
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be
TRSTB
Input
C1
Active low Test Reset (TRSTB). This signal provides an asynchronous TEMUX 84 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. TRSTB must be asserted during the power up sequence.
r,
20
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07
TDO
Output D1
Test Data Output (TDO). This signal carries test data out of the TEMUX 84 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress.
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25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
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In
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VDD1.8[19] VDD1.8[18] VDD1.8[17] VDD1.8[16] VDD1.8[15] VDD1.8[14] VDD1.8[13] VDD1.8[12] VDD1.8[11] VDD1.8[10] VDD1.8[9] VDD1.8[8] VDD1.8[7] VDD1.8[6] VDD1.8[5] VDD1.8[4] VDD1.8[3] VDD1.8[2] VDD1.8[1]
Power C2 Power (VDD1.8[19:1]). The VDD1.8[19:1] pins should D3 be connected to a well-decoupled +1.8V DC power J2 supply. R1 U3 AB2 AB9 Y12 Y15 AB19 N4 V20 U19 N21 K21 C22 C18 A13 B7
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77
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
VSS[69] VSS[68] VSS[67] VSS[66] VSS[65] VSS[64] VSS[63] VSS[62] VSS[61] VSS[60] VSS[59] VSS[58] VSS[57] VSS[56] VSS[55] VSS[54] VSS[53] VSS[52] VSS[51] VSS[50] VSS[49] VSS[48] VSS[47] VSS[46] VSS[45] VSS[44] VSS[43] VSS[42] VSS[41] VSS[40] VSS[39] VSS[38] VSS[37] VSS[36] VSS[35] VSS[34] VSS[33] VSS[32] VSS[31] VSS[30]
Ground C4 Ground (VSS3.3[69:1]). The VSS[69:1] pins should A12 be connected to GND. AA2 AA3 AA7 AB12 AB15 AB21 AB8 B4 C11 C17 C19 C3 D15 D19 D22 D5 D8 F1 G19 G4 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K3 K9 L10 L11 L12 L13 L14
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78
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Unconnected
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Unconnected
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VSS[29] VSS[28] VSS[27] VSS[26] VSS[25] VSS[24] VSS[23] VSS[22] VSS[21] VSS[20] VSS[19] VSS[18] VSS[17] VSS[16] VSS[15] VSS[14] VSS[13] VSS[12] VSS[11] VSS[10] VSS[9] VSS[8] VSS[7] VSS[6] VSS[5] VSS[4] VSS[3] VSS[2] VSS[1]
L21 L9 M10 M11 M12 M13 M14 M19 M4 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 T2 V21 V22 W21 Y11 Y14 Y17
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Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Notes on Pin Descriptions: 1. All TEMUX 84 inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels.
Co
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A1 These balls have no internal connections. They may B2 be left floating or tied to a static logic level. L4 P4 T19
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In
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79
25
Pin Name
Type
Pin Function No.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In
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6. Power to the VDD3.3 pins should be applied before power to the VDD1.8 pins is applied. Similarly, power to the VDD1.8 pins should be removed before power to the VDD3.3 pins is removed.
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da
5. All unused inputs should be connected to GROUND.
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14
4. Input A[12] has an internal pull-down resistor.
Se
3. Inputs CSB, RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.
pt
em
be
2. All TEMUX 84 outputs and bi-directionals have at least 2 mA drive capability. The bidirectional data bus outputs, D[7:0], have 4 mA drive capability. The outputs TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1], RGAPCLK/RSCLK[3:1], RDATO[3:1], RFPO/RMFPO[3:1], ROVRHD[3:1], TFPO/TMFPO/TGAPCLK[3:1], SBIACT, RECVCLK1, RECVCLK2, RECVCLK3, CASID[21:1], CCSID, MVID[21:1], TS0ID, TDO and INTB have 4 mA drive capability. The SBI outputs and telecom bus outputs, SDDATA[7:0], SDDP, SDPL, SDV5, SAJUST_REQ, LAV5, LAC1J1V1, LADATA[7:0], LADP, LAOE/LATPL and LAPL, have 8mA drive capability. The bidirectional SBI signal SDC1FP has 8mA drive capability.
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25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
80
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
9.1
Transparent Virtual Tributaries
Do wn lo
A TVT presented by the Telecom Drop bus must contain a valid V1/V2 pointer. The V1/V2 will be modified in the process of mapping the TVT into the SBI Drop Bus, which by definition has a SPE alignment equivalent to a pointer of 522 decimal. Tributary and path pointer justifications on the Telecom Drop Bus will result in corresponding rate justifications at the SBI Drop Bus as indicated by the SDPL signal. The SDV5 output will always indicate the V5 byte location.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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On the SBI Add Bus there are two methods of indicating transmit pointers. If the ETVTPTRDIS or EPTRBYP bit is logic 1, the SAV5 input must indicate the location of the V5 byte and the V1/V2 bytes need not be valid at the SBI Add Bus. If both ETVTPTRDIS and EPTRBYP bit are logic 0, the V1/V2 bytes at the SBI Add Bus must contain a pointer to the V5 byte. The Egress VTPPs accommodate the arbitrary alignment of the SBI and Telecom Add buses by encoding a new V1/V2 value and generating a LAV5 output pulse to match. The H1/H2 value is not encoded. The Telecom bus may be formatted as AU3s or as an AU4; the VTPPs will translate the AU3s to the AU4 format of the SBI bus.
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in
Transparent virtual tributaries (TVTs) are supported when performing VT1.5/TU11 or VT2/TU12 mapping into the Telecom Bus and the SBI Bus is being used. Conceptually, a TVT is passed straight from the Telecom Bus to the SBI Bus (and visa versa) with no knowledge of the mapping protocol or T1/E1 framing.
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In
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*
A single 44.736Mbit/s or 34.386Mbit/s stream. It may be a T3, E3 or clear channel. The 44.736Mbit/s data stream may be mapped into a SONET/SDH structure.
14
Se
pt
em
*
28 1.544Mbit/s or 21 2.048Mbit/s tributaries multiplexed into a DS3 or mapped directly into a SONET/SDH structure. The tributaries may be framed T1s, framed E1s, transparent virtual tributaries (TVTs) or clear channel. Optionally, the DS3 may be mapped into a SONET/SDH structure.
be
r,
The TEMUX 84 supports a total throughput of 155.52Mbit/s (including overhead) in both transmit (a.k.a. egress) and receive (a.k.a. ingress) directions. The bandwidth is divided into three approximately equal data streams, each independently configured relative to the others. Configurations include, but are not limited to:
20
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81
9
FUNCTIONAL DESCRIPTION
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
The frame pulse constraints of Section 12.2.3 must be adhered to when the TEMUX 84 is operating in transmux mode with the TelecomBus operating at 77.76 MHz.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
A specific register configuration sequence must be followed to enable transmux mode correctly. This sequence is defined in section 4.7 of the TEMUX 84 Programmer's Guide, PMC-2010270 Issue 3.
Co
nt e
nt Te a
Performance monitoring as documented in the T1/E1 Performance Monitoring section can be performed on the tributaries. In addition, HDLC channels and PRBS patterns may be monitored. With the exception of unframed PRBS reception, the performance monitoring assumes the tributaries are standard T1 or E1 data streams. On a per-tributary basis, the TXPMON context bit programmed through the RJAT Indirect Channel Data Register selects either the SONET/SDH mapper transmit or DS3 transmit tributary for performance monitoring.
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The correspondence between the DS3 tributaries and the SONET/SDH VT/TUs is provided in the Tributary Indexing section.
in
er
In
In the reverse direction, VT1.5/TU11s or VT2/TU12s are bit asynchronously demapped from the Telecom Drop bus. The 1.544 Mb/s or 2.048 Mb/s tributaries are jitter attenuated and multiplexed into a DS3, which is presented on the serial clock and data outputs.
co
n
Tu
es
The TEMUX 84 will receive a channelized DS3 stream from the serial clock and data inputs. It will frame up to the DS3 and de-multiplex the individual 1.544 Mb/s or 2.048 Mb/s tributaries. The tributaries are jitter attenuated, bit asynchronously mapped into VT1.5/TU11s or VT2/TU12s and presented on the Telecom Add bus. Byte synchronous mapping is not an option in transmux mode.
da
y,
14
Se
pt
em
Transmultiplexing ("transmux") is the operating mode that enables 1.544 Mb/s and 2.048 Mb/s unstructured tributaries to be exchanged between the SONET/SDH Telecom Bus and the DS3 line interface. It is enabled on a perSPE/DS3 basis by setting an SPE Configuration register's OPMODE_SPEx[2:0] bits to 010 and it's LINEOPT_SPEx[1:0] bits to 00. The system interface is unused in this mode.
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9.2
Transmultiplexing
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The Clock and Frame Synchronization Constraints section indicates constraints on bus alignments imposed by TVT support.
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
82
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
T1 framing can be performed on up to three sets of 28 tributaries. Each set of tributaries may be multiplexed into a DS3 or mapped into a SPE via VT1.5s/TU11s. The T1 framing function searches for the framing bit pattern in the standard Superframe (SF), SLC96 or Extended Superframe (ESF) framing formats. When searching for frame each of the 193 (SF or SLC96) or each of the 772 (ESF) framing bit candidates is simultaneously examined. The time required to acquire frame alignment to an error-free ingress stream, containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0), is dependent upon the framing format. For SF format, the T1 framer will determine frame alignment within 4.4ms 99 times out of 100. For SLC(R)96 format, the T1 framer will determine frame alignment within 13ms. For ESF format, the T1 framer will determine frame alignment within 15 ms 99 times out of 100. Once the T1 framer has found frame, the ingress data is continuously monitored for framing bit errors, bit error events (a framing bit error in SF or a CRC-6 error in ESF), and severely errored framing events. The performance data is accumulated for each tributary. The T1 framer also detects out-of-frame, based on a selectable ratio of framing bit errors. For ESF, out-of-frame declaration is based strictly on Frame Alignment Signal (F1-F6) bit errors; a new frame search is never initiated upon excessive CRC-6 errors.
9.3.1 Inband Code Detection The framer detects the presence of either of two programmable inband loopback activate and deactivate code sequences in either framed or unframed data streams (whether data stream is framed or unframed is not programmable) . The loopback codes will be detected in the presence of a mean bit error rate of up to 10-2. When the inband code is framed, the framing bits overwrite the code bits, thus appearing to the receiver as a 2.6x10-3 BER (which is within the tolerable BER of 10-2). Code indication is provided on the active high loopback activate (LBA) and loopback deactivate (LBD) status bits. Changes in these status bits result in the setting of corresponding interrupt status bits, LBAI and LBDI respectively, and can also be configured to result in the setting of a maskable interrupt indication.
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The framing function can also be disabled to allow reception of unframed data.
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9.3
T1 Framing
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
9.3.3 T1 Alarm Integration
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The presence of Yellow alarm is declared when the Yellow pattern has been received for 400 ms ( 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for 400 ms ( 50 ms). The presence of Red alarm is declared when an out-of-frame condition has been present for 2.55 sec ( 40 ms); the Red alarm is removed when the out-of-frame condition has been absent for 16.6 sec ( 500 ms). The presence of AIS alarm is declared when an out-offrame condition and all-ones in the PCM data stream have been present for 2.55
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The presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, SLC96 or ESF formats is detected and integrated in accordance with the specifications defined in ANSI T1.403 and TR-TSY-000191.
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Valid BOC are indicated through the BOCI status bit. The BOC bits are set to all ones (111111) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated or when a valid code goes away (i.e. the BOC bits go to all ones).
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Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). The receiver declares a received code valid if it has been observed for two consecutive times. The code is declared removed if two code sequences containing code values different from the detected code are received two consecutive times.
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The presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link channel in ESF framing format is detected, as defined in ANSI th T1.403 and in TR-TSY-000194. The 64 code (111111) is similar to the HDLC flag sequence and is used to indicate no valid code received.
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9.3.2 T1 Bit Oriented Code Detection
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The code sequence detection and timing is compatible with the specifications defined in T1.403, TR-TSY-000312, and TR-TSY-000303.
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The inband loopback activate condition consists of a repetition of the programmed activate code sequence in all bit positions for a minimum of 5.08 seconds ( 40 ms). The inband loopback deactivate condition consists of a repetition of the programmed deactivate code sequence in all bit positions for a minimum of 5.08 seconds ( 40 ms). Programmed codes can be from three to eight bits in length.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
84
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
By definition, AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all ones pattern and 0.15 seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in length in which, if the first bit is numbered bit 0, bits 3088, 3474 and 5790 are logical zeros and all other bits in the pattern are logical ones. AIS-CI is an unframed pattern, so it is defined for all framing formats.
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Once basic (or FAS) frame alignment has been found, the incoming PCM data stream is continuously monitored for FAS/NFAS framing bit errors, which are accumulated in a framing bit error counter dedicated to each tributary. Once CRC multiframe alignment has been found, the PCM data stream is continuously monitored for CRC multiframe alignment pattern errors and CRC-4 errors, which
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The E1 framing function searches for basic frame alignment, CRC multiframe alignment, and channel associated signaling (CAS) multiframe alignment in the incoming recovered PCM stream.
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E1 framing can be performed on up to three sets of 21 tributaries. Each set of tributaries may be multiplexed into a DS3 according to the ITU-T Rec. G.747 standard or mapped into a SPE via VT2s/TU-12s.
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E1 Framing
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AIS-CI is declared between 1.40 and 2.56 seconds after initiation of the AIS-CI signal and is deasserted 16.6 seconds after it ceases.
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RAI-CI is declared when a bit oriented code of "00111110 11111111" is validated (i.e. two consecutive patterns) while RAI (a.k.a. Yellow alarm) is declared. RAI-CI is cleared upon deassertion of RAI or upon 28 consecutive 40ms intervals without validation of "00111110 11111111".
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By definition, RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of 00000000 11111111 (right-to-left) with 90 ms of 00111110 11111111.
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The RAI-CI and AIS-CI alarms defined in T1.403 are detected reliably.
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9.3.3.1 Customer Interface Alarms
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CFA alarm detection algorithms operate in the presence of a 10-3 bit error rate.
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sec (40 ms); the AIS alarm is removed when the AIS condition has been absent for 16.6 sec (500 ms).
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
85
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
The E1 framer extracts the contents of the International bits (from both the FAS frames and the NFAS frames), the National bits, and the Extra bits (from timeslot 16 of frame 0 of the CAS multiframe). Moreover, the framer also extracts submultiframe-aligned 4-bit codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessor-accessible registers that are updated every CRC submultiframe. The E1 framer identifies the raw bit values for the Remote (or distant frame) Alarm (bit 3 in timeslot 0 of NFAS frames) and the Remote Signaling Multiframe (or distant multiframe) Alarm (bit 6 of timeslot 16 of frame 0 of the CAS multiframe). Access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 4 (provided the RAIC bit is logic 1) and 3 consecutive occurrences, respectively, as per Recommendation O.162. Detection of AIS and timeslot 16 AIS are provided. AIS is also integrated, and an AIS Alarm is indicated if the AIS condition has persisted for at least 100 ms. The out of frame (OOF=1) condition is also integrated, indicating a Red Alarm if the OOF condition has persisted for at least 100 ms. An interrupt may be generated to signal a change in the state of any status bits (INF, INSMF, INCMF, AIS or RED), and to signal when any event (RAI, RMAI, AISD, TS16AISD, COFA, FER, SMFER, CMFER, CRCE or FEBE) has occurred. Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe. Basic Frame Alignment Procedure The E1 framer searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2.
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are accumulated in a CRC error counter dedicated to each tributary. Once CAS multiframe alignment has been found, the PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1 framer also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based on user-selectable criteria. The reframe operation can be initiated by software, by excessive CRC errors, or when CRC multiframe alignment is not found within 400 ms.
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
If either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit FAS sequence check. This "hold-off" is done to ensure that new frame alignment searches are done in the next bit position, modulo 512. This facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the FAS. The algorithm provides robust framing operation even in the presence of random bit errors; the algorithm provides a 99.98% probability of finding frame alignment within 1 ms in the presence of 10-3 bit error rate and no mimic patterns. Once frame alignment is found, the INF context bit is set to logic 1, a change of frame alignment is indicated (if it occurred), and the frame alignment signal is monitored for errors occurring in the 7-bit FAS pattern and in bit 2 of NFAS frames, and the debounced value of the Remote Alarm bit (bit 3 of NFAS frames) is reported. Loss of frame alignment is declared if 3 consecutive FASs have been received in error or, additionally, if bit 2 of NFAS frames has been in error for 3 consecutive occasions. In the presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes.
* * *
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the CRC Frame Find Block is unable to find CRC multiframe alignment; or the CRC Frame Find Block accumulates excessive CRC evaluation errors ( 915 CRC errors in 1 second) and is enabled to force a re-frame under that condition.
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the software re-frame bit, REFR, in the T1/E1 Framer Indirect Channel Data registers is set to logic 1;
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The E1 framer can be forced to initiate a basic frame search at any time when any of the following conditions are met:
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3. Check that the correct 7-bit FAS is present in the assumed TS 0 byte of the next frame.
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2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed non-frame alignment sequence (NFAS) TS 0 byte is a logic 1;
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1. Search for the presence of the correct 7-bit FAS (`0011011');
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The algorithm finds frame alignment by using the following sequence:
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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Under the CRC-to-non-CRC interworking algorithm, if the E1 framer can achieve basic frame alignment with respect to the incoming PCM data stream, but is unable to achieve CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed to be a non CRC-4 interface. The details of this algorithm are illustrated in the state diagram in Figure 12.
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Once CRC multiframe alignment is found, the INCMF register bit is set to logic 1, and the E1 framer monitors the multiframe alignment signal (MFAS), indicating errors occurring in the 6-bit MFAS pattern, errors occurring in the received CRC and the value of the FEBE bits (bit 1 of frames 13 and 15 of the multiframe). The E1 framer declares loss of CRC multiframe alignment if basic frame alignment is lost. However, once CRC multiframe alignment is found, it cannot be lost due to errors in the 6-bit MFAS pattern.
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The E1 framer searches for CRC multiframe alignment by observing whether the International bits (bit 1 of TS 0) of NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms
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CRC Multiframe Alignment Procedure
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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NFAS found next fram e
FAS not found next fram e
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NFAS_Find
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FAS not found next fram e
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FAS_Find_2
FAS_Find_2_Par
FAS found next fram e
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Start 400m s tim er and 8m s tim er
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FAS found
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8m s expire and NOT(400m s expire)
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400m s expire
CR C MFA
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Reset BF A to m ost recently found alignm ent
CR CMFA_Par
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CRC to CRC Interworking
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CRCMFA_Par (Optional setting)
CRC to non-CRC Interworking
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Start 8m s tim er
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FAS_Find_1
FAS_Find_1_Par
NFAS not found next fram e
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3 consecutiv e FAS or NF AS errors; m anual refram e; or excessiv e C RC errors
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Figure 12
- CRC Multiframe Alignment Algorithm
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
When a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which is also the basic frame alignment corresponding to the newly found CRC multiframe alignment).
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Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. If, however, the 400 ms timer expires at any time during this procedure, the E1 framer stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In this mode, the E1 framer may be optionally set to either halt searching for CRC multiframe altogether, or may
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If the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. This search is performed in accordance with the Basic Frame Alignment procedure outlined above. However, this search does not immediately change the actual basic frame alignment of the system (i.e., PCM data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation).
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From an out of frame state, the E1 framer attempts to find basic frame alignment in accordance with the FAS/NFAS/FAS G.706 Basic Frame Alignment procedure outlined above. Upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared.
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The states of the primary basic framer and the parallel/offline framer in the E1 framer block at each stage of the CRC multiframe alignment algorithm are shown in Table 1.
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State FAS_Find_1 NFAS_Find FAS_Find_2 BFA CRC to CRC Interworking FAS_Find_1_Par NFAS_Find_Par FAS_Find_2_Par BFA_Par CRC to non-CRC Interworking
Out of Frame Yes Yes Yes No No No No No No No
Out of Offline Frame No No No No No Yes Yes Yes No No
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Table 1
- E1 framer Framing States
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
continue searching for CRC multiframe alignment using the established basic frame alignment. In either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once CRC-to-non-CRC interworking is declared: it is assumed that the established basic frame alignment at this point is correct.
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The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or additionally, if all the bits in time slot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of CAS multiframe alignment is also declared if basic frame alignment has been lost.
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This E1 framer also indicates the reception of TS 16 AIS when time slot 16 has been received with three or fewer zeros in each of two consecutive multiframe periods. The TS16AIS status is cleared when each of two consecutive signaling multiframe periods contain four or more zeros OR when the signaling multiframe signal is found.
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Once signaling multiframe alignment has been found, the E1 framer sets the INSMF context bit of the tributary to logic 1, and monitors the signaling multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe).
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Once the basic frame alignment has been found, the E1 framer searches for Channel Associated Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling multiframe alignment is declared when at least one non-zero time slot 16 bit is observed to precede a time slot 16 containing the correct CAS alignment pattern, namely four zeros ("0000") in the first four bit positions of timeslot 16.
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Signaling Frame Alignment
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When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting the AISD context bit to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit to be set to logic 0.
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AIS Detection
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PM8316 TEMUX 84
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The E1 framer can also be disabled to allow reception of unframed data.
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The Red alarm algorithm monitors occurrences of out of frame (OOF) over a 4 ms interval, indicating a valid OOF interval when one or more OOF indications occurred during the interval, and indicating a valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval with a valid OOF indication increments an interval counter which declares Red Alarm when 25 valid intervals have been accumulated. An interval with valid INF indication decrements the interval counter; the Red Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of frame alignment occurs.
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The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1 framer counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13 or more AISD indications (of a possible 16) have been received. Each interval with a valid AIS presence indication increments an interval counter which declares AIS Alarm when 25 valid intervals have been accumulated. An interval with no valid AIS presence indication decrements the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of a 10-3 mean bit error rate.
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The OOF and the AIS defects are integrated, verifying that each condition has persisted for 104 ms ( 6 ms) before indicating the alarm condition. The alarm is removed when the condition has been absent for 104 ms ( 6 ms).
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This E1 framer also detects the V5.2 link ID signal, which is detected when 2 out of 3 Sa7 bits are zeros. Upon reception of this Link ID signal, the V52LINKV context bit is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones.
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The E1 framer extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4] , Sa5[1:4] , Sa6[1:4] , Sa7[1:4] and Sa8[1:4]. The corresponding register values are updated upon generation of the CRC submultiframe interrupt.
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National Bit Extraction
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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Received data is placed into a 127-byte FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. The RHDL Indirect Channel Data Registers contain bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence end of message bytes written into the FIFO. The RHDL Indirect Channel Data Registers also indicates the abort, flag, and end of message status of the data
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The HDLC Receiver detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS).
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The HDLC Receiver is a microprocessor peripheral used to receive HDLC frames on the 4 kHz ESF facility data link or the E1 Sa-bit data link. A data link can also be extracted from any sub-set of bits within a single DS0.
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T1/E1 HDLC Receiver
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The transfer clock within the TEMUX 84 chip is generated precisely once per second (i.e. 19440000 SREFCLK cycles) if the AUTOUPDATE bit of the T1/E1 Framer Configuration and Status register is logic 1 or by writing to the Global PMON Update register with the FRMR bit set. Coincident with the counter transfer, a Performance Report Message (PRM) is transmitted for each T1 tributary for which the PRMEN context bit is logic 1.
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A bit error event (BEE) is defined as an F-bit error for SF and SLC96 framing format or a CRC-6 error for ESF framing format. A framing bit error (FER) is defined as an Fs or Ft error for SF and SLC96 and an Fe error for ESF framing format.
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CRC error events, Frame Synchronization bit error events, and Out Of Frame events, or optionally, Change of Frame Alignment (COFA) events are accumulated with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). When the transfer clock signal is applied, the counter values are transferred into holding registers and resets the counters to begin accumulating events for the interval. The counters are reset in such a manner that error events occurring during the reset are not missed. If the holding registers are not read between successive transfer clocks, the OVR context bit is asserted to indicate data loss.
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9.5
T1/E1 Performance Monitoring
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
9.7
T1/E1 Elastic Store (ELST)
The frame data is buffered in a two frame circular data buffer. Input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer. When the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane/transmit clock, the write pointer will catch up to the read pointer and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The subsequent frame is deleted. If the average frequency of the incoming data is less than the average frequency of the backplane/transmit clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The previous frame is repeated.
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For payload conditioning, the ingress ELST may optionally insert a programmable idle code into all channels when the framer is out of frame synchronization. This code is set to all 1's when the ELST is reset.
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To allow for the extraction of signaling information in the data channels, superframe identification is also passed through the ELST.
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When the ingress timing is recovered from the receive data, the ingress elastic store can be bypassed to eliminate the 2 frame delay.
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A slip operation is always performed on a frame boundary.
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In the egress direction, the Elastic Store is required in H-VIP mode or in SBI slave or locked modes when the transmit data is loop timed or referenced to one of the recovered clocks (RECVCLK1, RECVCLK2, RECVCLK3).
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In the ingress direction, the Elastic Store (ELST) synchronizes ingress frames to the common ingress H-MVIP clock and frame pulse (CMV8MCLK, CMVFP, CMVFPC) in H-MVIP modes. When using the SBI bus, the elastic store is required in locked or slave mode.
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Frame slip buffers exist in both the ingress and egress directions.
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just read from the FIFO. On end of message, the RHDL Indirect Channel Data Registers indicates the FCS status and if the packet contained a non-integer number of bytes.
3:
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
94
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
One superframe or signaling-multiframe of signal freezing is provided on the occurrence of slips. When a slip event occurs, output signaling for the entire superframe in which the slip occurred is frozen; the signaling is unfrozen when the next slip-free superframe occurs.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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9.9
T1/E1 Receive Per-Channel Control Data and signaling trunk conditioning may be applied on the ingress stream on a per-channel basis. Also provided is per-channel control of data inversion and the detection and generation of pseudo-random patterns. These operations occur on
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An interrupt is provided to indicate a change of signaling state on a per channel basis.
nt e
nt Te a
Control over timeslot signaling bit fixing and signaling debounce is provided on a per-timeslot basis.
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tm
in
Three superframes for ESF and six superframes for SLC96 and SF worth of signal are buffered to ensure that there is a greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones density out-of-frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With signaling debounce enabled, the per-channel signaling state must be in the same state for 2 ESF superframes or 4 SF/SLC96 superframes before appearing on the serial output stream.
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In
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In T1 mode, signaling bits are extracted from the received data streams for ESF, SLC96 and SF framing formats. The signaling states are optionally debounced and serialized onto the CASID[x] H-MVIP outputs or CAS bits within the SBI Bus structure. Debouncing is performed on the entire signaling state. This CASID[x] output is channel aligned with the MVID[x] output, and the signaling bits are repeated for the entire superframe, allowing downstream logic to reinsert signaling into any frame, as determined by system timing. The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5, 6, 7 and 8) in ESF framing format. In SF and SLC96 format, bits 5 and 6 contain the A and B bits from every second superfame and bits 7 and 8 contain the A and B bits from the alternate superframes. The four bits are updated every 24 frames and are debounced collectively.
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04
07
Channel associated signaling (CAS) is extracted from an E1 signaling multiframe or from ESF, SLC96 and SF T1 formats.
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95
9.8
T1/E1 Signaling Extraction
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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SLC96 is partially supported. The F-bits must be sourced from the system interface. To pass the F-bits transparently, the FDIS context bit must be set. Also, a superframe alignment must be provided to ensure the robbed-bit signaling is inserted in the correct frames relative to the F-bits. To ensure the
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9.10.1 SLC96
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The transmitter can be disabled for framing via the FDIS context bit.
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The F-bit may be passed transparently from either the H-MVIP or SBI interface. To support alignment of the robbed bit signaling to the F-bits, the C8MVFPB input may be redefined as a superframe alignment pulse.
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If the AUTOUPDATE bit of the T1/E1 Framer Configuration and Status register is logic 1, the T1 transmitter automatically sends an ANSI T1.403-formatted performance report on the T1 facility data link once per second.
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tm
in
A data link is provided for ESF mode. The data link sources include bit oriented codes and HDLC messages. If the T1_FDL_DIS context bit is logic 1, the data link is sourced from the F-bit position of the H-MVIP or SBI interface. Support is provided for the transmission of framed or unframed Inband Code sequences and transmission of AIS, Yellow, AIS-CI and RAI-CI (ESF only) alarm signals for all formats.
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In
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The transmitter provides per-channel control of idle code substitution, data inversion (either all 8 bits, sign bit magnitude or magnitude only), and zero code suppression. Three types of zero code suppression (GTE, Bell and "jammed bit 8") are supported and selected on a per-channel basis to provide minimum ones density control. Context bits provide per-channel control of robbed bit signaling and selection of the signaling source. All channels can be forced into a trunk conditioning state by the Master Trunk Conditioning (MTRK) context bit. The transmitter may source pseudo-random bit sequences (PRBS) in a selected subset of channels, while simultaneously monitoring the data from the system interface for PRBS errors.
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The T1 transmitter generates the 1.544 Mbit/s T1 data streams according to SF, SLC96 or ESF frame formats.
04
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9.10 T1 Transmitter
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the data after its passage through frame slip buffer, so that data and signaling conditioning may overwrite the trouble code.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
The E1 transmitter provides per-timeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle code substitution and signaling substitution) by use of the master trunk conditioning (MTRK) context bit. The transmitter may source pseudo-random bit sequences
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The E1 transmitter generates a 2048 kbit/s data streams according to ITU-T recommendations, providing individual enables for frame generation, CRC multiframe generation, and channel associated signaling (CAS) multiframe generation.
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9.11 E1 Transmitter
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Bit oriented codes are transmitted on the T1 Facility Data Link as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. When driving the T1 facility data link, the transmitted bit oriented codes have priority over any data transmitted except for ESF Yellow Alarm. The code to be transmitted is programmed by writing to the BOC code context bits where it is held until the latest code has been transmitted at least 10 times. If a second code is written before ten repetitions of the first have been transmitted, the second code will be transmitted immediately after the tenth transmission of the first code. If a third consecutive code is desired, its write must be delayed until the transmission of the second code has started, lest the third code overwrite the second.
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63 of the possible 64 bit oriented codes may be transmitted in the Facility Data Link (FDL) channel in ESF framing format, as defined in ANSI T1.403-1995. When transmission is disabled the FDL is set to all ones.
14
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9.10.2 T1 Bit Oriented Code Generation
em
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With an H-MVIP interface, the transmit elastic store cannot be bypassed, so the transmit clock must be locked to CTCLK which must be presented a clock that is locked to CMV8MCLK.
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20
04
When using the SBI interface, it is recommended the transmit frame slip buffer be bypassed and that the transmit clock be locked to the data stream (i.e. TJAT LOOPT and REFSEL context bits logic 0).
07
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framing is not corrupted, the timing must be configured to avoid controlled frame slips.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The HDLC transmitter then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. A second mechanism transmits data when the FIFO depth has reached a user configured upper threshold. The HDLC transmitter will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold has completed. In this mode,
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When enabled, the HDLC transmitter continuously transmits the flag sequence (01111110) until data is ready to be transmitted.
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tm
The HDLC transmitter provides a serial data link for the 4 kHz ESF facility data link or E1 Sa-bit data link. The data link may also be presented in any sub-set of bits within a selected DS0. The HDLC transmitter is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-CCITT frame check sequence (FCS) may be appended, followed by flags. If the HDLC transmitter data FIFO underflows, an abort sequence is automatically transmitted.
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9.12 T1/E1 HDLC Transmitters
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The National Use bits (Sa-bits) can be sourced from the National Bits Codeword context bits as 4-bit codewords aligned to the submultiframe. Only one of the E1 National Bits - SaX (where X = 4-8) can be modified at a given time with a userselectable 4-bit repeating code word. All remaining Sa-bits will have to be inserted from the system interface if they are to be modified. Setting the INDIS bit to the T1/E1 TXFRMR block enables this. Alternatively, the Sa-bits may individually carry data links sourced from the internal HDLC controller, or may be passed transparently from the MVED[x] inputs.
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04
Common Channel Signaling (CCS) is supported in time slots 15, 16 and 31. Support is provided for the transmission of AIS and TS16 AIS, and the transmission of remote alarm (RAI) and remote multiframe alarm signals.
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(PRBS) in a selected sub-set of channels, while simultaneously monitoring the data from the system interface for PRBS errors.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The jitter attenuators provide excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. In T1 mode, each jitter attenuator can accommodate up to 48 UIpp of input jitter at jitter frequencies above 4 Hz. For jitter frequencies below 4 Hz, more correctly called wander, the tolerance increases 20 dB per decade. In E1 mode each jitter attenuator can
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Jitter Characteristics
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The following describes the T1/E1 jitter attenuators in isolation. Other active functions such as SBI mapping, M13 multiplexing and SONET/SDH mapping may alter the jitter characteristics of the T1/E1 tributaries.
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The TEMUX 84 contains two separate jitter attenuators, one between the receive demultiplexed or demapped T1 or E1 link and the ingress interface and the other between the egress interface and the transmit T1 or E1 link to be multiplexed into DS3 or mapped into SONET/SDH. Each jitter attenuator receives jittered data and stores the stream in a FIFO timed to the associated clock. The jitter attenuated data emerges from the FIFO timed to the jitter attenuated clock. In the receive jitter attenuator, the jitter attenuated clock is referenced to the demultiplexed or demapped tributary receive clock. In the transmit jitter attenuator, the jitter attenuated transmit tributary clock feeding the M13 multiplexer or SONET/SDH mapper may be referenced to either the data stream, the CTCLK primary input, or the tributary receive clock.
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9.13 T1/E1 Receive and Transmit Digital Jitter Attenuators
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Abort characters can be continuously transmitted at any time by setting the ABT bit. During packet transmission, an underrun situation can occur if data is not written before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDRI interrupt.
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If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences.
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Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun.
04
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the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For T1 modes the jitter attenuator input jitter tolerance is 48 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 278 Hz. For E1 modes the input jitter tolerance is 48 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 369 Hz.
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Jitter Tolerance
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The jitter attenuators exhibit negligible jitter gain for jitter frequencies below 3.4 Hz, and attenuate jitter at frequencies above 3.4 Hz by 20 dB per decade in T1 mode. They exhibit negligible jitter gain for jitter frequencies below 5 Hz, and attenuates jitter at frequencies above 5 Hz by 20 dB per decade in E1 mode. In most applications the jitter attenuators will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through the jitter attenuators. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the waiting time jitter introduced by the multiplexing into DS3 or mapping into SBI or SONET/SDH. The jitter attenuator allows the implied T1 jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met. The jitter attenuator meets the E1 jitter attenuation requirements of the ITU-T Recommendations G.737, G.738, G.739 and G.742.
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accommodate up to 48 UIpp of input jitter at jitter frequencies above 5 Hz. For jitter frequencies below 5 Hz, more correctly called wander, the tolerance increases 20 dB per decade. In most applications, each jitter attenuator will limit jitter tolerance at lower jitter frequencies only. The jitter attenuator meet the stringent low frequency jitter tolerance requirements of AT&T TR 62411 and ITUT Recommendation G.823, and thus allow compliance with these standards and the other less stringent jitter tolerance standards cited in the references.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
100
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
07
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100
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48 62411Min
10 Jitter Amplitude (UI pp)
1.0
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28
Minimum Jitter Tolerance
acceptable 0.4
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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0.01 1
4.9
10
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100 300 1k Jitter Frequency (Hz)
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0.1
14
unacceptable
10k
25
100k
101
Figure 13
- Jitter Tolerance T1 Modes
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
07
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48 ITU-T G.823 Min
100 40
10 Jitter Amplitude (UI pp)
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1.5 1.0
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Minimum Jitter Tolerance
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unacceptable
acceptable 0.2
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The output jitter in T1 mode for jitter frequencies from 0 to 3.4 Hz is no more than 0.1 dB greater than the input jitter, excluding the residual jitter. Jitter frequencies above 3.4 Hz are attenuated at a level of 20 dB per decade, as shown in Figure 15.
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Jitter Transfer
In
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0.01 1
10
Tu
20
100 1k Jitter Frequency (Hz)
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0.1
14
2.4k
10k18k
3:
100k
102
25
Figure 14
- Jitter Tolerance E1 Modes
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
-10
Jitter Gain (dB)
62411 Max
-40
10
er
-50 1
3.4
20
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The output jitter in E1 mode for jitter frequencies from 0 to 5.0 Hz is no more than 0.1 dB greater than the input jitter, excluding the residual jitter. Jitter frequencies above 2.5 Hz are attenuated at a level of 20 dB per decade, as shown in Figure 16.
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350 100 1k Jitter Frequency (Hz)
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62411 Min
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14
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-20
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43802 Max
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Jitter Attenuator Response
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10k
20
04
100k
in
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3:
103
25
Figure 15
- Jitter Transfer T1 Modes
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
-10
Jitter Gain (dB)
-40
10
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-50 1
5
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40
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Frequency Range
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The guaranteed linear operating range for the jittered input clock is 2.048 MHz 266 Hz with worst case jitter (48 UIpp) and maximum SREFCLK frequency offset ( 50 ppm). The tracking range is 2.048 MHz 999 Hz with no jitter or SREFCLK frequency offset.
by
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The guaranteed linear operating range for the jittered input clock is 1.544 MHz 200 Hz with worst case jitter (48 UIpp) and maximum SREFCLK frequency offset ( 50 ppm). The tracking range is 1.544 MHz 997 Hz with no jitter or SREFCLK frequency offset.
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400 100 1k Jitter Frequency (Hz)
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-30
Jitter Attenuator Response
14
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-20
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unacceptable acceptable
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G.737, G.738, G.739, G.742 Max
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10k
07
100k
in
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3:
104
25
Figure 16
- Jitter Transfer E1 Modes
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
27 - 1 27 - 1
x7 + x3 + 1 with XOR in the feedback path x7 + x3 + 1 with XNOR in the feedback path
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The six generators can be programmed to generate any pseudo-random pattern with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in length. It also can generate the four DDS codes specified by Bellcore GR-819CORE. In addition, the pattern generator can insert single bit errors or a bit error rate between 10-1 to 10-7.
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In addition to the basic PRBS generators and receivers associated with each T1/E1 link, six full-featured pattern generator/detector pairs are available for association with any software selectable link. Any subset of bits within a frame (except the T1 F-bit) may be programmed to carry either a pseudo-random or fixed pattern.
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The detector auto-synchronizes to the expected PRBS pattern and accumulates the total number of bit errors in a 16-bit counter. The error count accumulates over the interval defined by writes to the Global PMON Update register. When a transfer is triggered, the holding register is updated, and the counter reset to begin accumulating for the next interval. The counter is reset in such a way that no events are missed. The data is then available until the next transfer.
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In
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220 - 1
x20 + x3 + 1
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220 - 1 (QRSS)
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x20 + x17 + 1 with zero suppression
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215 - 1
x15 + x14 + 1
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211 - 1
x11 + x9 + 1
14
Sequence Length
Polynomial
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The following pseudo random bit sequences are supported:
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The Pseudo Random Binary Sequence Generator/Detector (PRBS) is a software selectable PRBS generator and checker for 27-1, 211-1, 215-1 or 220-1 PRBS polynomials for use in the T1 and E1 links. PRBS patterns may be generated and monitored in both the transmit or receive directions for all T1 and E1 links simultaneously. The generator is capable of inserting single bit errors under microprocessor control.
20
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9.14 T1/E1 Pseudo Random Binary Sequence Generation and Detection (PRBS)
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
105
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
9.15 DS3/E3 Framing, Performance Monitoring and Multiplexing There are three identical instances of the DS3/E3 subsystem provided. It is important to note the subsystems are active simply by providing appropriate clocks; this is independent of the settings of the SYSOPT[1:0] and OPMODE_SPEx[2:0] register bits. From this observation, the following TEMUX 84 abilities arise: The TPOS/TDAT and TNEG/TMFP present data simply if a DS3/E3 transmit clock is present. This is independent of whether mapping of a DS3 into SONET/SDH is selected by LINEOPT_SPEx[1:0] register bits. The source of the clock is dependent on the SBICLKMODE, LOOPT and TICLK register bits. When T1/E1 Mapper/Multiplexer mode is selected via the OPMODE_SPEx[2:0] register bits, the DS3 multiplexing in the transmit direction occurs independent of the state of the LINEOPT_SPEx register bits. The same cannot be said of the receive direction; the demultiplexed T1/E1s are not presented on the system interface if LINEOPT_SPEx[1] is logic 1. The RDATO, RFPO/RMFPO and ROVRHD outputs present data simply if a receive DS3/E3 clock is present. The receive clock (RGAPCLK/RSCLK) will be associated with a demapped DS3 if the LINEOPT_SPEx[1:0] register bits are binary 01 or the transmit DS3/E3 if a diagnostic loopback is selected. Otherwise, it is derived from the RCLK input.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The six receivers can be programmed to check for the generated pseudo random pattern. The receivers can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. If a repetitive pattern is selected, the receiver will synchronize to any bit sequence that repeats with the programmed periodicity. A bit error accumulates when a bit disagrees with the original bit sequence synchronized to. The counters accumulate either over intervals defined by writes to the Pattern Detector registers or upon writes to the Global PMON Update Register. When a transfer is triggered, the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way that no events are missed. The data is then available in the holding registers until the next transfer.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
106
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Source and destination of the DS3/E3 clocks and data are dependent on configuration. Figure 17 is a simplified block diagram that illustrates the effect of the configuration of microprocessor accessible register bits. To preserve clarity, the registers that affect clock polarity or data format have been omitted. Figure 17 - DS/E3 Configuration Options
RGAPCLK/RSCLK, RDATO, RFPO/RMFPO, ROVRHD balls (always available) data from SONET/SDH DS3 demapper clock RPOS/RDAT and RNEG/RLCV balls 1 0 0 1 DS3 Framer 0
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1
M13 demux & 7 DS2 framers DS3/E3 perf. monitor
20
04
28 T1s or 21 E1s
RCLK ball
0 1
LINEOPT=01
DLOOP
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1
E3 Framer
one DS3 or E3
E3DS3B
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TDAT/TPOS & TNEG/TMFP
1 0 1
DS3 Clock
1
DS3 Tran
1 1 0 0
0 1
from SBI Drop Bus TFPI/TMFPI & TDATI balls
0
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To SONET/SDH DS3 mapper.
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TXSBI
0
M13 mux
1
1 1 0 0 E3DS3B
E3 Tran 1 0 0 1 PLOOP
1 0
TCLK
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0 LLOOP
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1 1 0 OPMODE = 011 or 100 LOOPT 0 DS3 or E3 clock from SBI Add Interface TICLK ball
by
LOOPT*(TCLK + UNF)
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
SBICLKMODE* TXSBI
07
DS3 or E3 clock to SBI Add Interface. Used if TXSBI*SBICLKMODE.
:4
- to T1/E1 sub-system if opmode = 00X - to SONET/SDH sub-system if opmode = 010 - to SBI Drop Bus if opmode = 011
28 T1s or 21 E1s
3:
25
*
The DS3/E3 performance monitoring capability only requires a DS3/E3 line rate clock to actively maintain alarm statuses and accumulate statistics.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
107
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Three instances of the DS3 Framer are independently programmed. From each the framed data is presented on RDATO[x], mapped into the SBI bus or may be demultiplexed to 28 DS1s or 21 E1s (ITU-T Rec. G.747). The DS3 Framer (DS3-FRMR) Block integrates circuitry required for decoding a B3ZS-encoded signal and framing to the resulting DS3 bit stream. The DS3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications. The DS3-FRMR decodes a B3ZS-encoded signal and provides indications of line code violations. The B3ZS decoding algorithm and the LCV definition can be independently chosen through software. A loss of signal (LOS) defect is also detected for B3ZS encoded streams. LOS is declared when inputs RPOS and RNEG contain zeros for 175 consecutive RCLK cycles. LOS is removed when the ones density on RPOS and/or RNEG is greater than 33% for 175 1 RCLK cycles. The framing algorithm examines five F-bit candidates simultaneously. When at least one discrepancy has occurred in each candidate, the algorithm examines the next set of five candidates. When a single F-bit candidate remains in a set, the first bit in the supposed M-subframe is examined for the M-frame alignment signal (i.e., the M-bits, M1, M2, and M3 are following the 010 pattern). Framing is declared, and out-of-frame is removed, if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. During the examination of the M-bits, the X-bits and P-bits are ignored. The algorithm gives a maximum average reframe time of 1.5 ms. While the DS3-FRMR is synchronized to the DS3 M-frame, the F-bit and M-bit positions in the DS3 stream are examined. An out-of-frame defect is detected when 3 F-bit errors out of 8 or 16 consecutive F-bits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration Register), or when one or more M-bit errors are detected in 3 out of 4 consecutive M-frames. The M-bit error criteria for OOF can be disabled by the MBDIS bit in the DS3 Framer Configuration register. The 3 out of 8 consecutive F-bits out-of-frame ratio provides more robust operation, in the presence of a high bit error rate, than the 3 out of 16 consecutive F-bits ratio. Either out-of-frame criteria allows an out-offrame defect to be detected quickly when the M-subframe alignment patterns or, optionally, when the M-frame alignment pattern is lost. Also while in-frame, line code violations, M-bit or F-bit framing bit errors, and Pbit parity errors are indicated. When C-bit parity mode is enabled, both C-bit parity errors and far end block errors are indicated. These error indications, as
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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9.15.1 DS3 Framer (DS3-FRMR)
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PM8316 TEMUX 84
well as the line code violation and excessive zeros indication, are accumulated over 1 second intervals with the Performance Monitor (DS3-PMON). Note that the framer is an off-line framer, indicating both OOF and COFA events. Even if an OOF is indicated, the framer will continue indicating performance monitoring information based on the previous frame alignment. Three DS3 maintenance signals (a RED alarm condition, the alarm indication signal, and the idle signal) are detected by the DS3-FRMR. The maintenance detection algorithm employs a simple integrator with a 1:1 slope that is based on the occurrence of "valid" M-frame intervals. For the RED alarm, an M-frame is said to be a "valid" interval if it contains a RED defect, defined as an occurrence of an OOF or LOS event during that M-frame. For AIS and IDLE, an M-frame interval is "valid" if it contains AIS or IDLE, defined as the occurrence of less than 15 discrepancies in the expected signal pattern (1010... for AIS, 1100... for IDLE) while valid frame alignment is maintained. This discrepancy threshold ensures the detection algorithms operate in the presence of a 10-3 bit error rate. For AIS, the expected pattern may be selected to be: the framed "1010" signal; the framed arbitrary DS3 signal and the C-bits all zero; the framed "1010" signal and the Cbits all zero; the framed all-ones signal (with overhead bits ignored); or the unframed all-ones signal (with overhead bits equal to ones). Each "valid" Mframe causes an associated integration counter to increment; "invalid" M-frames cause a decrement. With the "slow" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 127, which results in a detection time of 13.5 ms. With the "fast" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 21, which results in a detection time of 2.23 ms (i.e., 1.5 times the maximum average reframe time). RED, AIS, or IDLE are removed when the respective counter decrements to 0. DS3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is deasserted. Valid X-bits are extracted by the DS3-FRMR to provide indication of far end receive failure (FERF). A FERF defect is detected if the extracted X-bits are equal and are logic 0 (X1=X2=0); the defect is removed if the extracted X-bits are equal and are logic 1 (X1=X2=1). If the X-bits are not equal, the FERF status remains in its previous state. The extracted FERF status is buffered for 2 Mframes before being reported within the DS3 FRMR Status register. This buffer ensures a better than 99.99% chance of freezing the FERF status on a correct value during the occurrence of an out of frame.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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When the C-bit parity application is enabled, both the far end alarm and control (FEAC) channel and the path maintenance data link are extracted. Codes in the FEAC channel are detected by the Bit Oriented Code Detector (RBOC). HDLC messages in the Path Maintenance Data Link are received by the Data Link Receiver (RDLC). The DS3-FRMR can be enabled to automatically assert the RAI indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or RED, or AIS. The DS3-FRMR can also be enabled to automatically insert C-bit Parity FEBE upon detection of receive C-bit parity error. The DS3-FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the DS3-FRMR. Access to these registers is via a generic microprocessor bus.
9.15.3 DS3/E3 HDLC Receiver (RDLC)
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The RDLC is a microprocessor peripheral used to receive HDLC frames on the DS3 C-bit parity Path Maintenance Data Link, E3 G.832 Network Operator byte,
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Valid BOC are indicated through the RBOC Interrupt Status register. The BOC bits are set to all ones (111111) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones).
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Bit oriented codes are received on the Facility Data Link channel or FEAC channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). BOCs are validated when repeated at least 10 times. The receiver can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC context bit. The code is declared removed if two code sequences containing code values different from the detected code are received in a moving window of ten code periods.
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The presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link channel in ESF framing format is detected, as defined in ANSI T1.403 and in TR-TSY-000194 or in the DS3 C-bit parity far-end alarm and th control (FEAC) channel. The 64 code (111111) is similar to the HDLC flag sequence and is used to indicate no valid code received.
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9.15.2 DS3 Bit Oriented Code Detection
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* * * * *
line code violation (LCV) events
path parity error (CPERR) events far end block error (FEBE) events
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Due to the off-line nature of the DS3 and E3 Framers, PMON continues to accumulate performance metrics even while the framer has declared OOF.
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excess zeros (EXZS) framing bit error (FERR) events
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parity error (PERR) events
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The Performance Monitor (PMON) Block interfaces directly with the DS3 Framer (DS3-FRMR) and E3 Framer. Saturating counters are used to accumulate:
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9.15.4 DS3/E3 Performance Monitor Accumulator (DS3/E3-PMON)
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The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes.
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Received data is placed into a 128-byte FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.
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In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching.
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The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS).
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E3 G.832 General Purpose Communications Channel or E3 G.751 National Use bit.
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9.15.5 DS3 Transmitter (DS3-TRAN)
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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When enabled for C-bit parity operation, the FEAC channel is sourced by the bitoriented code transmitter. The path maintenance data link messages are sourced by the TDPR data link transmitter. The DS3-TRAN supports diagnostic modes in which it inserts parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, or all-zeros.
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A valid pair of P-bits is automatically calculated and inserted by the DS3-TRAN. When C-bit parity mode is selected, the path parity bits, and far end block error (FEBE) indications are automatically inserted.
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Status signals such as far end receive failure (FERF), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. FERF can also be automatically inserted on detection of any combination of LOS, OOF or RED, or AIS by the DS3-FRMR.
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The DS3 Transmitter (DS3-TRAN) Block integrates circuitry required to insert the overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats.
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Three DS3 transmitters are instantiated. Each may be programmed to provide framing for unchannelized data from TDATI[x] or the SBI bus, or framing for multiplexed T1s or E1s (ITU-T Rec. G.747).
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Whenever counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set.
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When counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. In addition, a register is provided to indicate changes in the PMON counters since the last accumulation interval.
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When an accumulation interval is signaled by a write to the PMON register address space or to the Global PMON Update register, the PMON transfers the current counter values into microprocessor accessible holding registers and resets the counters to begin accumulating error events for the next interval. The counters are reset in such a manner that error events occurring during the reset period are not missed.
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1.
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In each case, the DS3 transmitter drives the selected DS3 clock source onto the TCLK output pins of the DS3/E3 line side interface.
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Recovered DS3 clock from the RCLK[3:1] input pins. If the system interface is SBI, then TEMUX 84 is the SBI bus clock master, as in case 1 above. If the system interface is serial clock and data, TEMUX 84 derives TGAPCLK[3:1] from the recovered DS3 clock.)
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Integral DS3 clock synthesizer, which generates a gapped DS3 clock from the CLK52M input pin, in response to SBI bus timing justification requests from the link-layer device. TEMUX 84 is the SBI bus clock slave in this mode, and the SBI bus must be the system side option. External jitter attenuation is recommended when using this DS3 timing option.
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TICLK[3:1] input pins. If the system interface is SBI, then TEMUX 84 is the SBI bus clock master, and uses the SAJUST_REQ output signal to issue timing justification requests to the link-layer device. If the system interface is serial clock and data, TEMUX 84 derives TGAPCLK[3:1] from TICLK[3:1].)
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DS3 transmitter timing has three possible sources:
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9.15.6 DS3 Transmitter Timing Sources
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Bit oriented codes are transmitted on the DS3 Far-End Alarm and Control channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. The code to be transmitted is programmed by writing to the XBOC code registers when it is held until the latest code has been transmitted at least 10 times. An interrupt or polling mechanism is used to determine when the most recent code written the XBOC register is being transmitted and a new code can be accepted.
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63 of the possible 64 bit oriented codes may be transmitted in the DS3 C-bit parity Far-End Alarm and Control (FEAC) channel. The 64th code (111111) is similar to the HDLC Flag sequence and is used to disable transmission of any bit oriented codes. When transmission is disabled the FEAC channel is set to all ones.
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9.15.5.1
DS3 Bit Oriented Code Generation
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If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences.
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Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun.
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A second mechanism transmits data when the FIFO depth has reached a user configured upper threshold. The HDLC transmitter will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold has completed. In this mode, the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data.
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The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The HDLC transmitter then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. The HDLC transmitter will force transmission if the FIFO is filled up regardless of whether or not the packet has been completely written into the FIFO.
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When enabled, the HDLC transmitter continuously transmits the flag sequence (01111110) until data is ready to be transmitted.
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The HDLC transmitter provides a serial data link for the DS3 C-bit parity path maintenance data link, E3 G.832 Network Operator byte, E3 G.832 General Purpose Communications Channel or E3 G.751 National Use bit. The HDLC transmitter is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRCCCITT frame check sequence (FCS) may be appended, followed by flags. If the HDLC transmitter data FIFO underflows, an abort sequence is automatically transmitted.
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9.15.7 DS3/E3 HDLC Transmitters
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Abort characters can be continuously transmitted at any time by setting the ABT bit. During packet transmission, an underrun situation can occur if data is not written before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDRI interrupt.
9.15.9 M23 Multiplexer (MX23) The M23 Multiplexer (MX23) integrates circuitry required to asynchronously multiplex and demultiplex seven DS2 streams into, and out of, an M23 or C-bit Parity formatted DS3 serial stream. When multiplexing seven DS2 streams into an M23 formatted DS3 stream, the MX23 function performs rate adaptation to the DS3 by integral FIFO buffers. The C-bits are also generated and inserted. Software control is provided to transmit DS2 AIS and DS2 payload loopback requests. The loopback request is coded by
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The PRGD can be programmed to check for the generated pseudo random pattern. The PRGD can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. If a repetitive pattern is selected, the receiver will synchronize to any bit sequence that repeats with the programmed periodicity. A bit error accumulates when a bit disagrees with the original bit sequence synchronized to. The counters accumulate either over intervals defined by writes to the Pattern Detector registers or upon writes to the Global PMON Update Register. When a transfer is triggered, the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way that no events are missed. The data is then available in the holding registers until the next transfer.
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The PRGD can be programmed to generate any pseudo-random pattern with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert single bit errors or a bit error rate between 10-1 to 10-7.
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The Pseudo Random Pattern Generator/Detector (PRGD) block is a software programmable test pattern generator, receiver, and analyzer for the DS3/E3 payload. Patterns may be generated in the transmit direction, and detected in the receive direction. The patterns consume the entire payload; the overhead bits are ignored. Unframed patterns are not supported. Two types of ITU-T O.151 compliant test patterns are provided : pseudo-random and repetitive.
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9.15.8 DS3/E3 Pseudo Random Pattern Generation and Detection (PRGD)
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DS2 payload loopback can be activated or deactivated under software control. During payload loopback the DS2 stream being looped back still continues unaffected in the demultiplex direction to the DS2 Framer. All seven demultiplexed DS2 streams can also be replaced with AIS on an individual basis under register control or they can be configured to be replaced automatically on detection of out of frame, loss of signal, RED alarm or alarm indication signal.
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Depending on configuration, declaration of DS2 out-of-frame occurs when 2 out of 4 or 2 out of 5 consecutive F-bits are in error (These two ratios are recommended in TR-TSY-000009 Section 4.1.2) or when one or more M-bit errors are detected in 3 out of 4 consecutive M-frames. The M-bit error criteria for OOF can be disabled via the MBDIS bit in the DS2 Framer configuration register. Note that the DS2 framer is an off-line framer, indicating both OOF and
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The DS2 FRMR frames to a DS2 signal with a maximum average reframe time of less than 7 ms. Both the F-bits and M-bits must be correct for a significant period of time before frame alignment is declared. Once in frame, the DS2 FRMR provides indications of the M-frame and M-subframe boundaries, and identifies the overhead bit positions in the incoming DS2 signal.
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The DS2 Framer (DS2-FRMR) integrates circuitry required for framing to a DS2 bit stream and is directly compatible with the M12 DS2 application.
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9.15.10
DS2 Framer (DS2 FRMR)
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When demultiplexing seven DS2 streams from an M23 formatted DS3, the MX23 performs bit destuffing via interpretation of the C-bits. The MX23 also detects and indicates DS2 payload loopback requests encoded in the C-bits. As per ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7, the loopback command is identified as C3 being the inverse of C1 and C2. Because TR-TSY000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. As per TR-TSY-000009 Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for five successive M-frames.
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inverting one of the three C-bits (the default option is compatible with ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7). The MX23 also supports generation of a C-bit Parity formatted DS3 stream by providing an internally generated DS2 rate clock corresponding to a 100% stuffing ratio. Integrated M13 applications are supported by providing an internally generated DS2 rate clock corresponding to a 39.1% stuffing ratio.
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The DS2 FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the DS2 FRMR.
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DS2 M-bit and F-bit framing errors are indicated. These error indications are accumulated for performance monitoring purposes in internal, microprocessor readable counters. The performance monitoring accumulators continue to count error indications even while the framer is indicating OOF.
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The DS2 X-bit is extracted by the DS2 FRMR to provide an indication of far end receive failure. The FERF status is set to the current X/RAI state only if the two successive X/RAI bits were in the same state. The extracted FERF status is buffered for 6 DS2 M-frames before being reported within the DS2 FRMR Status register. This buffer ensures a virtually 100% probability of freezing the FERF status in a valid state during an out of frame occurrence. When an OOF occurs, the FERF value is held at the state contained in the last buffer location corresponding to the previous sixth M-frame. This location is not updated until the OOF condition is deasserted. Meanwhile, the last four of the remaining five buffer locations are loaded with the frozen FERF state while the first buffer location corresponding to the current M-frame is continually updated every Mframe based on the above FERF definition. Once correct frame alignment has been found and OOF is deasserted, the first buffer location will contain a valid FERF status and the remaining five buffer locations are enabled to be updated every M-frame.
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The RED alarm and alarm indication signal are detected by the DS2 FRMR in 9.9 ms for DS2 format. The framer employs a simple integration algorithm (with a 1:1 slope) that is based on the occurrence of "valid" DS2 M-frame intervals. For the RED alarm, a DS2 M-frame is said to be a "valid" interval if it contains a RED defect, defined as the occurrence of an OOF event during that M-frame. For AIS, a DS2 M-frame is said to be a "valid" interval if it contains AIS, defined as the occurrence of less than 9 zeros while the framer is out of frame during that Mframe. The discrepancy threshold ensures the detection algorithm operates in the presence of bit error rates of up to 10-3. Each "valid" DS2 M-frame causes an integration counter to increment; "non-valid" DS2 M-frame intervals cause a decrement. RED or AIS is declared if the associated integrator count saturates at 53, resulting in a detection time of 9.9 ms. RED or AIS declaration is deasserted when the associated count decrements to 0.
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COFA. Error events continue to be indicated even when the FRMR is indicating OOF, based on the previous frame alignment.
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When demultiplexing four DS1 streams from an M12 formatted DS2, the MX12 performs bit destuffing via interpretation of the C-bits. The MX12 also detects and indicates DS1 payload loopback requests encoded in the C-bits. As per ANSI T1.107 Section 7.2.1.1 and TR-TSY-000009 Section 3.7, the loopback command is identified as C3 being the inverse of C1 and C2. Because TR-TSY000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. As per TR-TSY-000009 Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for five successive M-frames. DS1 payload loopback can be activated or deactivated under software control. During payload loopback the DS1 stream being looped back still continues unaffected in the demultiplex direction. The second and fourth demultiplexed DS1 streams are logically inverted. All four demultiplexed DS1 streams can be replaced with AIS on an individual basis or can be configured for automatic replacement with AIS on detection of out of frame or RED alarm conditions.
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Similar functionality is supplied for supporting ITU-T Recommendation G.747. Software control is provided to transmit Remote Alarm Indication (RAI), 6312 kbit/s AIS, and the reserved bit. A diagnostic option is provided to invert the transmitted frame alignment signal and parity bit.
Co
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When multiplexing four DS1 streams into an M12 formatted DS2 stream, the MX12 function performs logical inversion on the second and fourth tributary streams. Rate adaptation to the DS2 is performed by integral FIFO buffers, controlled by timing circuitry. The FIFO buffers accommodate in excess of 5.0 UIpp of sinusoidal jitter on the DS1 clocks for all jitter frequencies. X, F, M, and C bits are also generated and inserted by the timing circuitry. Software control is provided to transmit Far End Receive Failure (FERF) indications, DS2 AIS, and DS1 payload loopback requests. The loopback request is coded by inverting one of the three C-bits (the default option is compatible with ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7).Two diagnostic options are provided to invert the transmitted F or M bits.
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20
The M12 Multiplexer (MX12) integrates circuitry required to asynchronously multiplex and demultiplex four DS1 streams into, and out of, an M12 formatted DS2 serial stream as defined in ANSI T1.107 Section 7. The M12 multiplexer also supports the ITU-T Rec. G.747 standard for the multiplexing of three 2048 kbit/s streams into a 6312 kbit/s stream.
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9.15.11
M12 Multiplexer (MX12)
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When demultiplexing three 2048 kbit/s streams from a G.747 formatted 6312 kbit/s stream, bit destuffing is performed via interpretation of the C-bits. Tributary payload loopback can be activated or deactivated under software control. Although no remote loopback request has been defined for G.747, inversion of the one of the C-bits, as selected by the Loopback Code Select Register, triggers a loopback request detection indication in anticipation of Recommendation G.747 refinement. All three demultiplexed 2048 kbit/s streams can be replaced with AIS on an individual basis. 9.15.12 E3 Framer
* *
the Trail Trace bytes;
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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the FEBE bit for accumulation in PMON; the Payload Type bits and buffers them so that they can be read by the microprocessor; the Timing Marker bit and asserts the Timing Marker indication when the value of the extracted bit has been in the same state for 3 or 5 consecutive frames;
nt e
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the FERF bit and indicates an alarm when the FERF bit is a logic 1 for 3 or 5 consecutive frames. The FERF indication is removed when the FERF bit is a logic 0 for 3 or 5 consecutive frames;
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In G.832 E3 format, the E3-FRMR extracts:
tm
While in-frame, the E3-FRMR also extracts various overhead bytes and processes them according to the framing format selected:
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The E3-FRMR searches for frame alignment in the incoming serial stream based on either the G.751 or G.832 formats. For the G.751 format, the E3-FRMR expects to see the selected framing pattern error-free for three consecutive frames before declaring frame alignment. For the G.832 format, the E3-FRMR expects to see the selected framing pattern error-free for two consecutive frames before declaring frame alignment. Once the frame alignment is established, the incoming data is continuously monitored for framing bit errors and byte interleaved parity errors (in G.832 format).
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Three instances of the E3 Framer are independently programmed to frame to 34368 kbit/s frame formats. From each, the framed data is presented on RDATO[x] or mapped into the SBI bus.
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20
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In G.751 E3 mode, the E3-FRMR extracts:
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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E3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of
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Loss of signal is LOS is declared when no marks have been received for 32 consecutive bit periods. Loss of signal is de-asserted after 32 bit periods during which there is no sequence of four consecutive zeros.
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The E3-FRMR detects the presence of AIS in the incoming data stream when less than 8 zeros in a frame are detected while the framer is OOF in G.832 mode, or when less than 5 zeros in a frame are detected while OOF in G.751 mode. This algorithm provides a probability of detecting AIS within a single frame in the presence of a 10-3 BER as 92.9% in G.832 and 98.0% in G.751. After five frames, the probability of detection rises to >99.999% for both formats.
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The E3-FRMR declares out of frame alignment if the framing pattern is in error for four consecutive frames. The E3-FRMR is an "off-line" framer, where all frame alignment indications, all overhead bit indications, and all overhead bit processing continue based on the previous alignment. Once the framer has determined the new frame alignment, the out-of-frame indication is removed and a COFA indication is declared if the new alignment differs from the previous alignment.
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the National Use reserved bit (bit 12 of the frame) for further processing in the HDLC receiver when the RNETOP bit in the E3 Data Link Control register is logic 0. Optionally, an interrupt can be generated when the National Use bit changes state.
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14
*
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*
the Remote Alarm Indication bit (bit 11 of the frame) and indicates a Remote Alarm when the RAI bit is a logic 1 for 3 or 5 consecutive frames. Similarly, the Remote Alarm is removed when the RAI bit is logic 0 for 3 or 5 consecutive frames;
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20
04
07
*
the General Purpose Communication Channel byte for processing by the HDLC receiver when the RNETOP bit in the E3 Data Link Control register is logic 0.
:4
3:
25
*
the Network Operator byte for processing by the HDLC receiver when the RNETOP bit in the E3 Data Link Control register is logic 1;
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In G.832 E3 format, the E3-TRAN:
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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inserts the Payload Type bits based on the register value set by the microprocessor; inserts the Tributary Unit multiframe indicator bits either via the TOH overhead stream or by register bit values set by the microprocessor; inserts the Timing Marker bit via a register bit;
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inserts the FEBE bit, which is set to logic 1 when one or more BIP-8 errors are detected by the receive framer. If there are no BIP-8 errors indicated by the E3-FRMR, the E3-TRAN sets the FEBE bit to logic 0;
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inserts the FERF bit via a register bit or, optionally, when the E3-FRMR declares OOF, or when the loss of cell delineation (LCD) defect is declared;
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inserts the Trail Trace bytes;
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*
inserts the BIP-8 byte calculated over the preceding frame;
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The E3-TRAN generates the frame alignment signal and inserts it into the incoming serial stream based on either the G.751 or G.832 formats. All overhead and status bits in each frame format can be individually controlled by register bits. While in certain framing format modes, the E3-TRAN generates various overhead bytes according to the following:
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The E3 Transmitter (E3-TRAN) Block integrates circuitry required to insert the overhead bits into an E3 bit stream and produce an HDB3-encoded signal. The E3-TRAN is directly compatible with the G.751 and G.832 framing formats.
14
Se
pt
Three E3 transmitters provide framing insertion for 34368 kbit/s unchannelized data from TDATI[3:1] or the SBI bus.
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9.15.13
E3 Transmitter
20
The E3-FRMR can also be enabled to automatically assert the RAI/FERF indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or AIS. The E3-FRMR can also be enabled to automatically insert G.832 FEBE upon detection of receive BIP-8 errors.
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Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is de-asserted.
25
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In G.751 E3 mode, the E3-TRAN :
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E3 transmitter timing has three possible sources:
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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2.
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1.
TICLK[3:1] input pins. If the system interface is SBI, then TEMUX 84 is the SBI bus clock master, and uses the SAJUST_REQ output signal to issue timing justification requests to the link-layer device. If the system interface is serial clock and data, TEMUX 84 derives TGAPCLK[3:1] from TICLK[3:1].)
Integral E3 clock synthesizer, which generates a gapped E3 clock from the CLK52M input pin, in response to SBI bus timing justification requests from the link-layer device. TEMUX 84 is the SBI bus clock slave in this mode, and the SBI bus must be the system side option. External jitter attenuation is recommended when using this E3 timing option.
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9.15.13.1
E3 Transmitter Timing Sources
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Further, the E3-TRAN can provide insertion of bit errors in the framing pattern or in the parity bits, and insertion of single line code violations for diagnostic purposes.
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optionally identifies the tributary justification bits and stuff opportunity bits as either overhead or payload for payload mappings that take advantage of the full bandwidth.
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inserts the National Use reserved bit (bit 12 of the frame) either as a fixed value through a register bit or from the HDLC transmitter as configured by the TNETOP bit in the E3 Data Link Control register and the NATUSE bit in the E3 TRAN Configuration register;
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*
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inserts the Remote Alarm Indication bit (bit 11 of the frame) either via a register bit or, optionally, when the E3-FRMR declares OOF;
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20
04
*
inserts the General Purpose Communication Channel (GC) byte from the TDPR block when the TNETOP bit in the E3 Data Link Control register is logic 0; otherwise, the byte is set to all ones.
07
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3:
25
*
inserts the Network Operator (NR) byte from the TDPR block when the TNETOP bit in the E3 Data Link Control register is logic 1; otherwise, the NR byte is set to all ones. All 8 bits of the Network Operator byte are available for use as a datalink;
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9.16 Tributary Payload Processor (VTPP) Each one of three tributary payload processors (VTPP) processes the virtual tributaries within an STS-1, AU3, or TUG3. The VTPP can be configured to process either VT1.5s or VT2s within an STS-1 or either TU11s or TU12s within an AU3 or TUG3. The number of tributaries managed by each VTPP ranges from 21 (when configured to process all VT2s or equivalently all TU12s) to 28 (when configured to process all VT1.5s or equivalently all TU11s).
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The Payload Type label carried in the MA byte of the G.832 E3 stream is also extracted. The label is used to ensure that the adaptation function at the trail termination sink is compatible with the adaptation function at the trail termination source. The Payload Type label is check for consistency between consecutive multiframes. A Payload Type label received unchanged for five frames is accepted for comparison with the copy previously written into the TTB by the external microprocessor. Alarms are raised to indicate reception of unstable and mismatched Payload Type label bits.
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The Trail Trace Buffer (TTB) extracts and sources the trail trace message carried in the TR byte of the G.832 E3 stream. The message is used by the OS (operating system) to prevent delivery of traffic from the wrong source and is 16 bytes in length. The 16-byte message is framed by the PTI Multiframe Alignment Signal (TMFAS = 'b10000000 00000000). One bit of the TMFAS is placed in the most significant bit of each message byte. In the receive direction, the extracted message is stored in the internal RAM for review by an external microprocessor. By default, the byte of a 16-byte message with its most significant bit set high will be written to the first location in the RAM. The extracted trail trace message is checked for consistency between consecutive multiframes. A message received unchanged three or five times (programmable) is accepted for comparison with the copy previously written into the internal RAM by the external microprocessor. Alarms are raised to indicate reception of unstable and mismatched messages. In the transmit direction, the trail trace message is sourced from the internal RAM for insertion into the TR byte by the E3-TRAN.
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9.15.14
E3 Trail Trace Buffer
20
In each case, the E3 transmitter drives the selected E3 clock source onto the TCLK output pins of the DS3/E3 line side interface.
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3.
Recovered E3 clock from the RCLK[3:1] input pins. If the system interface is SBI, then TEMUX 84 is the SBI bus clock master, as in case 1 above. If the system interface is serial clock and data, TEMUX 84 derives TGAPCLK[3:1] from the recovered E3 clock.)
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The Tributary payload processor is used in both the ingress and egress data paths. In the egress direction the pointer interpreter section of the VTPP can be bypassed on a per tributary basis to allow for pointer generator in the absence of valid pointers which is necessary when mapping floating transparent virtual tributaries from the SBI bus.
The multiframe alignment sequence in the path overhead H4 byte is monitored for the bit patterns of 00, 01, 10, 11 in the two least significant bits. If an unexpected value is detected, the primary multiframe will be kept, and a second multiframe process will, in parallel, check for a phase shift. The primary process will enter out of multiframe state (OOM). A new multiframe alignment is chosen, and OOM state is exited when four consecutive correct multiframe patterns are detected. Loss of multiframe (LOM) is declared after residing in the OOM state at the ninth H4 byte without re-alignment. In counting to nine, the out of sequence H4 byte that triggered the transition to the OOM state is counted as the first. A new multiframe alignment is chosen, and LOM state is exited when four consecutive correct multiframe patterns are detected. Changes in multiframe alignments are detected and reported.
9.16.3 Payload Buffer
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The payload buffer is a bank of FIFO buffers. It is synchronous in operation and is based on a time-sliced RAM. The three 19.44 MHz clock cycles in each 6.48 MHz period are shared between the read and write operations. The pointer interpreter writes tributary payload data and the V5 tag into the payload buffer. A 16 byte FIFO buffer is provided for each of the (up to 28) tributaries. Address
Co
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The pointer interpreter processes the incoming pointers (V1/V2) as specified in the references. The pointer value is used to determine the location of the tributary path overhead byte (V5) in the incoming TUG3 or STS-1 (AU3) stream.
nt Te a
The pointer interpreter is a time-sliced state machine that can process up to 28 independent tributaries. The state vector is saved in RAM as directed by the incoming timing generator. The pointer interpreter processes the incoming tributary pointers such that all bytes within the tributary synchronous payload envelope can be identified and written into the unique payload first-in first-out buffer for the tributary in question. A marker that tags the V5 byte is passed through the payload buffer. The incoming timing generator directs the pointer interpreter to the correct payload buffer for the tributary being processed.
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9.16.2 Pointer Interpreter
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9.16.1 Incoming Multiframe Detector
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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9.17 Receive Tributary Path Overhead Processor (RTOP) Each one of three tributary path overhead processors (RTOP) monitors the outgoing stream of the tributary payload processor (VTPP) and processes the tributaries within an STS-1, AU3, or TUG3. The RTOP can be configured to process all the VT1.5s or VT2s that can be carried in an STS-1 or all the TU11s
Co
nt e
The pointer generator is a time-sliced state machine that can process up to 28 independent tributaries. The state vector is saved in RAM at the address associated with the current tributary. The pointer generator fills the outgoing tributary synchronous payload envelopes with bytes read from the associated FIFO in the payload buffer for the current tributary. The pointer generator creates pointers in the V1-V3 bytes of the outgoing data stream. The marker that tags the V5 byte that is passed through the payload buffer is used to align the pointer. The outgoing timing generator directs the pointer generator to the FIFO in the payload buffer that is associated with the tributary being processed. The pointer generator monitors the fill levels of the payload buffers and inserts outgoing pointer justifications as necessary to avoid FIFO spillage. Normally, the pointer generator has a FIFO dead band of two bytes. The dead band can be collapse to one so that any incoming pointer justifications will be reflected by a corresponding outgoing justification with no attenuation. Signals are output by the pointer generator that identify outgoing V5 bytes and the tributary synchronous payload envelopes. On a per tributary basis, tributary path AIS and tributary idle (unequipped) can be inserted as controlled by microprocessor accessible registers. The idle code is selectable globally for the entire VC3 or TUG3 to be all-zeros or all-ones. It is also possible to force an inverted new data flag on individual tributaries for the purpose of diagnosing downstream pointer processors. Tributary path AIS is automatically inserted into outgoing tributaries if the pointer interpreter detects tributary path AIS on the corresponding incoming tributary.
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The pointer generator does not encode an H1/H2 value. The H1 and H2 byte contents are only valid on the Telecom Add bus when the Egress VTPP is bypassed.
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1. The pointer generator block generates the tributary pointers (V1/V2) as specified in the references. The pointer value is used to determine the location of the tributary path overhead byte (V5) on the outgoing stream.
20
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9.16.4 Pointer Generator
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information is also passed through the payload buffer to allow FIFO fill status to be determined by the pointer generator.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The tributary path signal label (PSL) found in the tributary path overhead byte (V5) is processed. An incoming PSL is accepted when it is received unchanged for five consecutive multiframes. The accepted PSL is compared with the associated provisioned value. The PSL match/mismatch state is determined by the following:
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nt e
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Tributary path remote defect indication (RDI) and remote failure indication (RFI) are detected by extracting bit 8 and bit 4 respectively of the tributary path overhead byte (V5). The RDI is recognized when bit 8 of the V5 byte is set high for five or ten consecutive multiframes while RFI is recognized when bit 4 of V5 is set high for five or ten consecutive frames. The RDI and RFI bits may be treated as a two-bit code word. A code change is only recognized when the code is unchanged for five or ten frames.
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Tributary path BIP-2 errors are detected by comparing the tributary path BIP-2 bits in the V5 byte extracted from the current multiframe, to the BIP-2 value computed for the previous multiframe. BIP-2 errors may be accumulated on a block or nibble basis as controlled by software configurable registers. Far end block errors (FEBEs) are detected by extracting the FEBE bit from the tributary path overhead byte (V5).
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The error monitor block contains a set of 12-bit counters that are used to accumulate tributary path BIP-2 errors, and a set of 11-bit counters to accumulate far end block errors (FEBE). The contents of the counters may be transferred to a holding RAM, and the counters reset under microprocessor control.
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9.17.1 Error Monitor
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The RTOP provides tributary performance monitoring of incoming tributaries. Bit interleaved parity of the incoming tributaries is computed and compared with the BIP-2 code encoded in the V5 byte of the tributary. Errors between the computed and received values are accumulated. RTOP also accumulates far end block error codes. Incoming path signal label is debounced and compared with the provisioned value. Path signal label unstable, path signal label mismatch and change of path signal label event are identified.
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or TU12s that can be carried in an AU3 or TUG3. The number of tributaries managed by each RTOP ranges from 21 (when configured to process all VT2s or all TU12s) to 28 (when configured to process all VT1.5s or all TU11s).
3:
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000 000 000 001 001 001 XXX 000, 001 XXX 000, 001 XXX 000, 001
000 001 XXX 000 000 001
Match
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Mismatch Match Match
Mismatch Match Match
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Mismatch
20
Mismatch
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Expected PSL
Accepted PSL
PSLM State
3:
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25
Table 2
- Path Signal Label Mismatch State
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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An extracted message is declared the accepted message, if it is received unchanged for 3 multiframes. The accepted message is compared with the locally provisioned expected message. A tributary trace identifier mismatch alarm (TIM) is asserted when the accepted and expected messages differ. Conversely, TIM is negated when the messages are identical. An interrupt is optionally generated upon a change in the TIM state. Messages of all-zeros bytes cannot become accepted and, therefore, have no effect on the TIM state. The RTTB also monitors for tributary trace unstable conditions. Each time a tributary trace message that is received differs from the previous message, the unstable counter is incremented by one. The tributary trace unstable alarm (TIU) is asserted when the unstable counter reaches eight. The unstable counter is
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The tributary trace message of each tributary is extracted form the J2 (J1 in TU3 mode) byte. It is written to the internal buffer corresponding to the tributary. The internal buffer may behave as a simple circular buffer, or optionally, be synchronized to the framing pattern embedded in the message. For a 16-byte trail trace identifier, the first byte is identified by a logic one in the most significant bit. For a 64-byte tributary trace message, the last two bytes are set to the ASCII characters for carriage-return (CR) and linefeed (LF).
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When configured for SONET compatible operation, each one of three receive tributary trace buffers (RTTB) processes the tributary trace message of all the tributaries in an STS-1 stream. Each of the seven tributary groups (VT groups) may be independently configured to accept any of the four tributary types (VT1.5, VT2, VT3, and VT6). The RTTB extracts tributary trace message from each tributary and stores it in one of a set of internal buffers. The RTTB may be configured for SDH compatible operation. The incoming stream may carry an AU3 of an STM1 stream or a TUG3 in an AU4 of an STM1 stream.
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9.18 Receive Tributary Trace Buffer (RTTB)
pt
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Each time an incoming PSL differs from the one in the previous multiframe, the PSL unstable counter is incremented. Thus, a single bit error in the PSL in a sequence of constant PSL values will cause the counter to increment twice, once on the errored PSL and again on the first error-free PSL. The incoming PSL is considered unstable when the counter reaches five. The counter is cleared when the same PSL is received for five consecutive multiframes.
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XXX 000, 001
YYY
Mismatch
3:
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25
Expected PSL
Accepted PSL
PSLM State
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9.19 Receive Tributary Bit Asynchronous Demapper (RTDM)
Table 3
- Asynchronous T1 Tributary mapping
24 bytes - 8I J2 C1C2OOOOIR 24 bytes - 8I Z6 C1C2OOOOIR 24 bytes - 8I
C1C2RRRS1S2R 24 bytes - 8I
R: Fixed Stuff bit - set to logic `0' or `1'
S: Stuff Opportunity bit - when stuff control bit is `0', stuff opportunity is I bit
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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O: Overhead I: T1 payload information
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C: Stuff Control bit - set to logic `1' for stuff indication
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RRRRRRIR
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Each one of three Receive Tributary Demappers (RTDM) demaps up to 28 T1 or 21 E1 bit asynchronous mapped signals from an STS-1 SPE, TUG3 within a STM-1/VC4 or STM-1 VC3 payload. The bit asynchronous T1 mapping consists of 104 octets every 500 s (2 KHz) and is shown in Table 3. The bit asynchronous E1 mapping consists of 140 octets every 500us and is shown in Table 4.
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cleared and the unstable alarm negated when the extracted message remains unchanged for enough multiframes to meet the acceptance criteria. An interrupt is optionally generated upon a change in the TIU state.
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C1C2OOOORR 32 bytes - 8I R Z6 C1C2OOOORR
S2I I I I I I I 31 bytes - 8I
C: Stuff Control bit - set to logic `1' for stuff indication
O: Overhead
ed
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
The RTDM buffers the tributary synchronous payload envelope bytes of the incoming tributaries in individual FIFOs to accommodate tributary pointer justifications. The RTDM performs majority voting on the tributary stuff control (C1, C2) bits. If the majority of each set of the stuff control bits indicate a stuff operation, then the associated stuff opportunity bit (S1, S2) will not carry T1 or E1 payload.
Co
nt e
I: E1 payload information
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m
S: Stuff Opportunity bit - when stuff control bit is `0', stuff opportunity is I bit
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R: Fixed Stuff bit - set to logic `0' or `1'
tm
in
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C1C2RRRRRS1
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Z7
es
R
da
32 bytes - 8I
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14
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be
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J2
20
R
04
32 bytes - 8I
07
R
:4
3:
130
V5
25
Table 4
- Asynchronous E1 Tributary Mapping
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
Given that frame alignment is provided by the mapping function, the T1/E1 framer doesn't provide the frame alignment for the system interface. If the tributary `F' bit position contains valid framing information, the T1/E1 framer may be used for performance and alarm monitoring.
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by
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Byte synchronous demapping is enabled on a per-tributary basis by setting the ENBL bit through the Byte Synchronous Demapping Tributary Control RAM Indirect Access Data register and by bypassing the receive jitter attenuator by setting the RJATBYP bit through the RJAT Indirect Channel Data register.
nt Te a
m
Each one of three Receive Tributary Byte Synchronous Demappers demaps up to 28 T1 or 21 E1 byte synchronous mapped signals from an STS-1 SPE, TUG3 within a STM-1/VC4 or STM-1 VC3 payload. The demapping is done in accordance with ITU-T Recommendation G.709 and ANSI T1.105. If byte synchronous tributaries are being demapped from a VC-3, the Ingress VTPP must not be bypassed and the OTUG3 bit of the SONET/SDH Master Ingress VTPP Configuration register must be logic 1.
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In
9.20 Receive Tributary Byte Synchronous Demapper
co
n
The RTDM optionally acts as a time switch. When time switching is enabled, the association of timeslots on the system interface (SBI or H-MVIP) to incoming tributaries is software configurable. There are two pages in the time switch configuration RAM. One page is software selectable to be the active page and the other the stand-by page. The configuration in the active page is used to switch incoming tributaries. The stand-by page can be programmed to the next switch configuration. Change of page selection is effected immediately. The one constraint on switch configuration is that the all the remapped tributaries in an SPE must be of the same type (T1 or E1). Also, if at least one tributary in a TUG3 or VC-3 is a byte synchronously demapped T1, no bit asynchronously demapped TU12 is allowed.
Tu
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14
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be
The RTDM, in cooperation with the T1/E1 jitter attenuator, attenuates jitter introduced by pointer justification events. The T1/E1 jitter attenuator may be bypassed, in which case an external device may use the SBI Link Rate Octet generated by RTDM to determine the clock phase. When a pointer justification is detected, the RTDM issues evenly spaced 1/12 UI T1 adjustments or 1/9 UI E1 adjustments encoded in the SBI Link Rate Octet.
r,
20
04
07
:4
3:
Conversely, if the majority of the stuff control bits indicate a data operation, the appropriate stuff opportunity bit(s) will carry T1 or E1 payload.
25
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
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Table 5
J1 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R
- Asynchronous DS3 mapping to STS-1 (STM-0/AU3)
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The asynchronous DS3 mapping consists of 9 rows every 125 s (8 KHz). Each row contains 621 information bits, 5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication channel bits. Fixed stuff bytes are used to fill the remaining bytes. The asynchronous DS3 mapping is shown in Table 5.
nt Te a
RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII
ar
tm
25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I
in
er
In
The DS3 Mappers do not support the mapping of DS3s into an AU4 via TUG-3s. Therefore, the Telecom Drop bus must be configured for AU-3s when demapping DS3s. For bit asynchronous E1/T1s to coexist with mapped DS3s, either the ING_TUG3 bits of the RTDM Indirect Ingress Tributary Data register must be logic 0 or the ITUG3 bit of the SONET/SDH Master Ingress VTPP Configuration must be logic 0 depending on whether the Ingress VTPP is bypassed. For byte synchronous E1/T1s to coexist with mapped DS3s, the Ingress VTPP cannot be bypassed.
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2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R
n
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CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR
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14
Each one of three DS3 Mapper DROP Side (D3MD) blocks demaps a DS3 signal from an STS-1 (STM-0/AU3) payload. The demapped DS3 is presented to the DS3 framer and subsequently presented on RDAT[x]. Optionally, it is mapped into the SBI bus or demultiplexed into 28 DS1s or 21 E1s.
Se
pt
26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I
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9.21 DS3 Mapper Drop Side (D3MD)
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2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R
20
Signaling, if present, may be dealt with in two ways for T1. By default, the T1 framer attempts to find frame and extracts the signaling from the robbed bit signaling positions. Alternately, the values encoded in the S1S2S3S4 bit positions are presented on the system interface verbatim without debounce or freezing if the RAWSIG bit programmed through the SIGX Indirect Channel Data registers is logic 1. This is programmed on a per-tributary basis. For E1, the signaling is extracted from "Multiframe alignment signal" byte.
04
07
CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS
:4
3:
25
STS
nt e
POH
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
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S: Stuff Opportunity bit - when stuff control bit is `0', stuff opportunity is I bit O: Overhead communication channel
P (p) M (0) M (1) M (0)
D D D
F (1) F (1) F (1)
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D D D
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P (p)
D
F (1)
D
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X (1)
D
F (1)
D
C (0) C (0) C (0) C (0) C (0)
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X (1)
D
F (1)
D
C (0)
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In
Table 6
- DS3 AIS format.
D D D D D D
co
Given a path signal label mismatch (PSLM) or path signal label unstable (PSLU), the D3MD ignores the STS-1 (STM-0/AU3) SPE and writes a DS3 AIS pattern to the elastic store. In addition, the desynchronization algorithm assumes a nominal ratio of data to stuff bits carried in the S bits (1 out of 3 S bits is assumed to be an information (data) bit). DS3 AIS is shown in Table 6.
F (0) F (0) F (0) F (0) F (0) F (0)
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D D D D D D
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The D3MD performs majority vote on the received C-bits. If 3 out of 5 C-bits are `1's, the associated S bit is interpreted as a stuff bit. If 3 out of 5 C-bits are `0's, the associated S bit is interpreted as an Information bit. The information bits are written to an elastic store and the Fixed Stuff bits (R) are ignored.
C (0) C (0) C (0) C (0) C (0) C (0)
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D D D D D D
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9.21.1 DS3 Demapper
F (0) F (0) F (0) F (0) F (0) F (0)
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I: DS3 payload information
20
D D D D D D
04
C (0) C (0) C (0) C (0) C (0) C (0) D D D D D D
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F (1) F (1) F (1) F (1) F (1) F (1)
C: Stuff Control bit - set to logic `1' for stuff indication
3:
D D D D D D F (0) D C (0) D F (1) D
133
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C (0)
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F (0)
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C (0)
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* *
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
Co
valid M-frame alignment bits (M-bits), M-subframe alignment bits (F-bits), and parity bit of the preceding M-frame (P-bits). The two P-bits are identical, either both are zeros or ones. all the C-bits in the M-frame are set to zeros the X-bits are set to ones
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25
R: Fixed Stuff bit - set to logic `0' or `1'
AM
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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Table 7 illustrates the gap patterns used to generate the desynchronized DS3 clock under the normal, DS3 AIS, faster and slower status. The faster pattern is used to drain the elastic store to avoid overflows. The slower pattern is used to allow the elastic store to fill to avoid underflows.
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The resulting output DS3 clock requires an external DS3 jitter attenuator circuit if it is to be used as a DS3 reference clock to an external LIU or the PM73122 AAL1gator32 ATM SAR device.
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When using the 44.928 MHz CLK52M clock, the DS3 clock is generated using a fixed 8 KHz interval. The 8KHz interval is subdivided into 9 rows. Each row contains either 621 or 622 clock periods. The CLK52M contains 624 cycles per row. To generate 621 pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap + 207 clocks + 1 clock gap is used. To generate 622 pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap + 208 clocks is used.
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The Desynchronizer monitors the Elastic Store level to control the de-stuffing algorithm to avoid overflow and underflow conditions. The Desynchronizer assumes a 44.928 MHz clock (provided via input CLK52M).
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9.21.3 DS3 Desynchronizer
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Data is read out of the Elastic Store using a divide by 8 version of the input CLK52M clock. If an overflow or underflow condition occurs, an interrupt is optionally asserted and the Elastic Store read and write address are reset to the startup values (logically 180 degrees apart).
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14
Se
pt
The elastic store block is provided to compensate for frequency differences between the DS-3 stream extracted from the STS-1 (STM-0/AU3) SPE and the CLK52M clock input. The DS3 Demapper extracts I bits from the STS-1 (STM-0/AU3) SPE and writes the bits into a 128 bit (16 byte) elastic store. Eight bytes are provided for SONET/SDH overhead (3 bytes for TOH, 1 byte for a positive stuff, 1 byte for POH) and DS3 reserve stuffing bits (2 bytes for R bits, and 3 overhead bits which is rounded-up to 1 byte). The remaining 8 bytes are provided for path pointer adjustments.
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04
07
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9.21.2 DS3 Demapper Elastic Store
3:
134
25
*
the information bit (84 Data bits with repeating sequence of 1010..)
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
The TTOP inserts the tributary trail trace identifier (TTI) into the J2 byte. Each tributary is provided with a 64-byte buffer to store the identifier. To transmit a 16byte message, one must write four identical copies to the buffer. One shadow buffer is available for temporary replacement of a selected transmitted TTI while the 64-byte identifier buffer is being updated. Data is retrieved sequentially from the active buffer at each J2 byte position. No CRC insertion is performed; any CRC must be written into the trail trace buffer. The shadow buffer can be
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
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The TTOP computes the BIP-2 code in the current tributary SPE and inserts the result into the BIP-2 bits of the V5 byte in the next tributary SPE. The tributary path signal label in the V5 byte of each tributary can be sourced from internal registers. The tributary far end block error bit in the V5 byte of each tributary is inserted based of the BIP error count detected at a companion RTOP block. The tributary remote failure indication and remote defect indication bits in the V5 or the Z7 byte of each tributary is inserted based on the tributary alarm status of the companion RTOP TSB.
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When configured for SONET compatible operation, the TTOP inserts the four tributary path overhead bytes (V5, J2, Z6, and Z7) to each tributary. The TTOP may also be configured for SDH compatible operation. The incoming STM-1 stream may carry three AU3s or an AU4 with three TUG3s.
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Each one of three Transmit Tributary Path Overhead Processors (TTOP) generates the path overhead for up to 28 VT1.5/TU-11s or 21 VT2/TU-12s.
n
Tu
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9.22 Transmit Tributary Path Overhead Processor (TTOP)
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9
622
14
8
621
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7
621
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6
622
622 621 622 622
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5
621
622
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4
621
621
20
3
622
622
04 r,
2
621
621
07
1
621
621
:4
Row Number
Normal or DS3 AIS
Run Faster
Run Slower 621 621 622 621 621 621 621 621 621
3:
25
135
Table 7
- DS3 desynchronizer clock gapping algorithm.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
programmed with new messages without timing constraints when inactive. An inactive 64-byte identifier buffer can also be programmed with new messages without timing constraints. Programming for TTI buffers is done one buffer at a time by first programming the shadow buffer, switching to the shadow buffer for the desired tributary, updating the desired tributary identifier buffer and finally switching back from the shadow buffer to the tributary buffer. Switching between the shadow buffer and normal buffer is synchronized to the start of each identifier on a per-tributary basis. 9.23 Transmit Remote Alarm Processor (TRAP)
-
bit 8 of the V5 byte equals bit 5 of the Z7 byte,
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
If the FORCEEN bit of the TRAP Control register is logic 1 then bit 8 of V5 (plus bit 5 of Z7 if ERDI) reflects the state of the RDI bit of the TRAP Control register and the ARDI bit of the TRAP Control register sets bit 6 of Z7 if ERDI. If FORCEEN is logic 0, the source for RDI-V and RFI-V can be any one of the RADEAST input, the RADWEST input or Telecom Drop bus alarms. The TRAP may be configured to insert tributary remote defect indications (RDI-V), tributary remote fault indications (RFI-V) and tributary remote error indications (REI-V) based on alarms detected in tributaries received on the Telecom Drop bus, LDDATA[7:0]. The contents of the SONET/SDH Master
Co
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if byte synchronous mapping is being used, bit 4 of V5 will equal the value programmed through the Byte Synchronous Mapping Tributary Control Indirect Access Data register; otherwise, it will be logic 0.
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bit 7 of the Z7 byte is always the complement of bit 6 of the Z7 byte, and
ar
tm
in
Two methods of encoding tributary remote alarms are supported, as selected on a per-tributary basis by the ERDI bits of the TRAP Control registers and TTOP Control registers. If the ERDI bits for a tributary are logic 0, RDI-V is transmitted by setting bit 8 of the V5 byte to logic 1 and RFI-V is transmitted by setting bit 4 of the V5 byte to logic 1. Bits 6 and 7 of the Z7 will be zeros. If the ERDI bits for a tributary are logic 1, extended RDI is effected. The triggers for ERDI-V are programmable, but the following is always true if ERDI is configured:
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In
co
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When configured for SONET compatible operation, each one of three TRAP SONET/SDH Transmit Remote Alarm Processors processes remote alarm indications of tributaries in an STS-3 stream. The virtual tributaries within an STS-1 stream may be configured to accept either VT1.5 or VT2 tributary types. The TRAP may also be configured for SDH compatible operation. The incoming STM-1 stream may carry three AU3s or an AU4 with three TUG3s.
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14
Se
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be
r,
20
04
07
:4
3:
25
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Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
The tributary mapper is a time-sliced state machine which uses a payload buffer as an elastic store. The T1 or E1 streams are read from the payload buffer, and mapped into VT1.5 Payloads and VT2 Payloads using bit asynchronous mapping only. The Tributary Mapper compensates for phase and frequency offsets using bit stuffing. A jitter-reducing control loop is used to monitor the Payload Buffer depth and reduce mapping jitter to 1.0 UI. To reduce mapping jitter even further, a
Co
nt e
nt Te a
Each one of three Transmit Tributary Mapper blocks bit asynchronously maps up to 28 T1 or 21 E1 streams into an STS-1 SPE, TUG3 in a STM-1/VC4 or STM1/VC3 payload. The TTMP compensates for any frequency differences between the incoming individual serial bit rates and the available STS-1 or STM-1/VC3 payload capacity. The asynchronous T1 mapping consists of 104 octets every 500 s (2 KHz). The asynchronous E1 mapping consists of 140 octets every 500 s (2 KHz). Refer to the RTDM block for a description of the asynchronous T1 and E1 mappings.
m
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9.24 Transmit Tributary Bit Asynchronous Mapper (TTMP)
In
The TRAP provides selection between the Telecom Drop bus alarms and the two remote serial alarm ports for the source of remote alarm status on a per-tributary basis. By default, all three sources are disabled. Tributaries in any of the three sources of remote alarms can be mapped to arbitrary tributaries in the outgoing data stream. The mapping is configured through the TRAP Indirect Remote Alarm Page Address, TRAP Indirect Remote Alarm Tributary Address and TRAP Indirect Datapath Tributary Data registers. A valid TU designation written via the TRAP Indirect Datapath Tributary Data register is all that is required to enable the alarms for the outgoing tributary specified by the TRAP Indirect Remote Alarm Tributary Address register. Although it is possible to have any subset of the three sources enabled, it is usual to have only one of the three sources enabled for a particular tributary.
co
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14
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em
be
In all cases, the RDI-V and RFI-V state will be sent for a minimum of 10 multiframes before changing, unless a higher priority alarm is required.
r,
20
Alternatively, the TRAP may also be configured to extract RDI-V, RFI-V and REIV from two independent serial remote alarm ports, RADEAST and RADWEST.
04
07
Tributary Remote Defect Indication Control register determine which alarms affect the state of bit 8 of V5 and (if ERDI is set) bit 5 of Z7. The contents of the SONET/SDH Master Tributary Auxiliary Remote Defect Indication Control register determine which alarms affect the state of bit 6 of Z7 if ERDI is set.
:4
3:
25
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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9.25 Transmit Tributary Byte Synchronous Mapper Each one of three Transmit Tributary Mapper blocks byte synchronously maps up to 28 T1 or 21 E1 streams into an STS-1 SPE, TUG3 in a STM-1/VC4 or STM1/VC3 payload. The mapping is done inaccordance with ITU-T Recommendation G.709 and ANSI T1.105. If byte synchronous tributaries are being mapped into a VC-3, the Egress VTPP must not be bypassed and the ITUG3 bit of the SONET/SDH Master Egress VTPP Configuration register must be logic 1. Byte synchronous mapping is enabled on a per-tributary basis by setting the ENBL bit through the Byte Synchronous Mapping Tributary Control RAM Indirect Access Data register, by bypassing the transmit jitter attenuator by setting the TJATBYP bit through theTJAT Indirect Channel Data register and by disabling the egress VTPP pointer interpretation via the EPTRBYP or ETVTPTRDIS bits. By default the T1/E1 framer inserts valid framing into the T1 `F' bit and E1 TS0. The T1 signaling received from the system interface is encoded into the S1S2S3S4 bit positions. Signaling is also inserted into the robbed bit signaling positions as enabled by the SIGC bits programmed through the TPCC Indirect Channel Data registers. For E1, the signaling insertion is independent of the mapping.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
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The TTMP outputs the STS-1, TUG3 in a STM-1/VC4 or STM-1/VC3 with the bit asynchronous mapped T1s or E1s onto an internal bus for further processing by the Transmit Tributary Payload Processor block.
14
Se
pt
The Tributary Mapper may optionally act as a time switch. When Time Switch Enable is active, the association of Tributary Mapper VT Payloads to logical FIFO data streams is software configurable. There are two pages in the time switch configuration RAM. One page is software selectable to be the active page and the other the stand-by page. The configuration in the active page is used to associate outgoing VT Payloads to logical FIFOs. The stand-by page can be programmed to the next switch configuration. Change of page selection is synchronized to incoming stream frame boundaries. When Time Switch Enable is inactive, the association of outgoing VT Payloads to logical FIFOs is fixed.
em
be
r,
20
04
07
:4
3:
dither technique is inserted between the control loop and the stuff bit generator resulting in an acceptable desynchronizer mapping jitter of about 0.3 UI.
25
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9.26.1 DS3 Mapper Serializer High speed serial data from the DS3-TRAN block is deserialized and written into the Elastic Store.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
9.26.2 DS3 Mapper Elastic Store The elastic store block is provided to compensate for frequency differences between the DS3 stream from the DS3-TRAN block and the STS-1 (STM-0/AU3) SPE capacity. The DS3 Serializer writes data into the elastic store at the
Co
nt e
nt Te a
m
The DS3 Mappers do not support the mapping of DS3s into an AU4 via TUG-3s. Therefore, the Telecom Add bus must be configured for AU-3s when demapping DS3s. For bit asynchronous E1/T1s to coexist with mapped DS3s, either the EGR_TUG3 bits of the TTMP Indirect Egress Tributary Address register must be logic 0 or the OTUG3 bit of the SONET/SDH Master Egress VTPP Configuration must be logic 0 depending on whether the Egress VTPP is bypassed. For byte synchronous E1/T1s to coexist with mapped DS3s, the Egress VTPP cannot be bypassed.
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Each one of three DS3 Mapper ADD Side (D3MA) blocks maps a DS3 signal into an STS-1 (STM-0/AU3) payload and compensate for any frequency differences between the incoming DS3 serial bit rate (TICLK) and the available STS-1 (STM-0/AU3) SPE mapped payload capacity. The asynchronous DS3 mapping consists of 9 rows every 125 s (8 KHz). Each row contains 621 information bits, 5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication channel bits. Fixed stuff bytes are used to fill the remaining bytes. Please refer to section 9.21 for a description of the DS3 mapping.
n
Tu
es
da
y,
14
Se
9.26 DS3 Mapper ADD Side (D3MA)
pt
em
To avoid introducing jitter, it is recommended that one avoid VT pointer justifications. If transmit timing is derived from the SBI Add bus data rate, SBI bus pointer movements should be avoided. If transmit timing is locked to CTCLK, then CTCLK should be locked to SREFCLK.
be
r,
20
04
The byte synchronous mapping protocol does not provide the capability to perform individual bit stuffs; rate adaptation is achieved through VT pointer justifications. A pointer justification introduces 8 UI of jitter. No special techniques are employed to shape the frequency spectrum of this jitter.
07
:4
3:
25
139
9.25.1 Jitter
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Row Number
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Table 8
- DS3 synchronizer bit stuffing algorithm. Normal or DS3 AIS S S I S S I S S I Run Faster S S I S I I S I I Run Slower S S I S S S S S S
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
nt e
nt Te a
1 2 3 4 5 6 7 8 9
m
tm
The DS3 synchronizer uses a fixed bit leaking algorithm which leaks 8 bits of phase buildup in 500 s. The 8 kHz STS-1 (STM-0/AU3) frame interval is subdivided into 9 rows. Each row contains one stuff opportunity. Table 8 illustrates the stuffing implementation where S means stuff bit and I means an information bit (DS3 data).
in
er
In
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n
Tu
The DS3 Synchronizer performs the mapping of the DS3 into the STS-1 (STM-0/AU3) SPE. The DS3 Synchronizer monitors the Elastic Store level to control the stuffing algorithm to avoid overflow (i.e. run faster) and underflow (i.e. run slower) conditions. The fill level of the elastic store is monitored and stuff opportunities in the DS3 mapping are used to center the Elastic Store. To consume a stuff opportunity, the five C-bits on a row are set to ones and the S bit is used to carry an DS3 information bit. When the S bit is not used to carry information, the C-bits on the row are set to zeros.
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da
y,
14
Se
pt
em
9.26.3 DS3 Synchronizer
be
The Elastic store is 128 bits (16 bytes) to allow for a fixed read/write pointer lag of 7 bytes (3 bytes for TOH, 1 byte for POH, 2 bytes for R bits, and 3 overhead bits which is rounded-up to 1 byte). Four bytes are also added on either side for positive and negative threshold detection.
r,
20
04
07
TICLK/8 rate while data is read out at the stuffed STS-1 (STM-0/AU3) byte rate. If an overflow or underflow condition occurs, an interrupt is optionally asserted and the Elastic Store read and write address are reset to the startup values (logically 180 degrees apart).
:4
3:
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
140
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Figure 18
- Egress Clock Slave
Tu
co
n
es
The Egress H-MVIP System Interface (Figure 18) provides system side H-MVIP access for up to 84 T1 or 63 E1 transmit streams. There are three separate interfaces for data, CAS signaling and CCS signaling. The H-MVIP signaling interfaces can be used in combination with the SBI interface in certain applications. Control of the system side interface is global to TEMUX 84 and is selected through the SYSOPT[1:0] bits in the Global Configuration register. The system interface options are H-MVIP, SBI bus and SBI bus with CAS or CCS HMVIP.
da
- H-MVIP
TRANSMITTER
in
CASED[1:21] CCSED[1:3] CMVFPB CMVFPC CMV8MCLK Egress System Inte rface
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MVED[1 :21]
In
CTCLK
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14
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be
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9.27 Egress H-MVIP System Interface
20
The D3MA outputs the STS-1 (STM-0/AU3) with the mapped DS3 onto the Line Add bus, LADATA[7:0].
tm
ELST Elastic Store
Inputs Tim ed to CMV8MCLK
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
Twenty-one H-MVIP data signals, MVED[1:21], share pins with the SBI inputs to provide H-MVIP access for up to 2016 data channels. The H-MVIP mapping is fixed such that each group of four nearest neighbor T1 or E1 links make up the individual 8.192 Mbit/s H-MVIP signal. This mode is selected when the SYSOPT[1:0] bits in the Global Configuration register are set to H-MVIP.
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When Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP egress interface multiplexes up to 2016 channels from 84 T1s or 63 E1s, up to 2016 channel associated signaling (CAS) channels from 84 T1s or 63 E1s and common channel signaling from up to 84 T1s or 63 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization.
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T1/E1Tran smitter: Frame Generation, Alarm Insertio n, Signaling Insertion, Trunk Conditioning
TJAT Digital PLL TJAT FIFO
04
07
Under microprocessor control, the incoming DS3 stream can be overwritten with the framed DS3 AIS. When asserting DS3 AIS, a nominal stuff pattern is used as illustrated above. Please refer to the D3MD functional description section for a description of the DS3 AIS frame.
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AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
to DS3 Multiplexer or SONET/SDH Mapper
141
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
The option exists to transmit at a rate locked to the CTCLK input, to a selected recovered clock or to be looped timed. Regardless of transmit timing source, the transmit elastic store can not be bypassed. To avoid controlled frame slips, the source of the transmit timing needs to be traceable to the source of the CMV8MCLK input. A separate twenty-one signal H-MVIP interface is for access to the channel associated signaling for 2016 channels. The CAS H-MVIP interface is time division multiplexed exactly the same way as the data channels. The CAS HMVIP is synchronized with the H-MVIP data channels when SYSOPT[1:0] is set to H-MVIP mode. Over a T1 or E1 multi-frame, the four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each CAS nibble (ABCD bits) out to a full byte in parallel with each data byte. Optionally, the third and fourth bit of each byte may be used as inband control of whether CAS signalling is inserted or whether the timeslot is 64 kbit/s clear channel. The CAS H-MVIP interface can be used in parallel with the SBI Add bus as an alternative method for accessing the CAS bits while data transfer occurs over the SBI bus. This is selected when the SYSOPT[1:0] bits in the Global Configuration register are set to "SBI Interface with CAS or CCS H-MVIP Interface". A separate H-MVIP interface consisting of three signals is used to time division multiplex the common channel signaling (CCS) for all T1s and E1s and additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSED[1:3], is not multiplexed with any other pins. CCSED[1:3] can be used in parallel with the Clock Slave:H-MVIP mode when SYSOPT[1:0] is set to "H-MVIP Interface" or in parallel with the SBI Add bus when SYSOPT[1:0] is set to "SBI Interface with CAS or CCS H-MVIP Interface". The TS16 CCS and V5 channels for E1 tributaries and channel 24 CCS for T1 tributaries can be enabled when the CCS16EN, CCS15EN, CCS31EN and/or CCSEN context bits are set to logic 1 through the T1/E1 Transmitter Indirect Channel Data Registers. When accessing the CAS or CCS signaling via the H-MVIP interface in parallel with the SBI interface a transmit signaling elastic store is used to adapt any timing differences between the data interface and the CAS or CCS H-MVIP interface. 9.28 Ingress System H-MVIP Interface
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
The Ingress System Interface (Figure 19) provides H-MVIP access for up to 84 T1 or 63 E1 receive streams. When enabled for 8.192 Mbit/s H-MVIP there are three separate interfaces for data and signaling. The H-MVIP signaling interfaces can be used in combination with the SBI interface in certain applications. Control
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tm
in
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In
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n
Tu
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14
Se
pt
em
be
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20
04
07
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3:
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
142
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
20
CASID[1:21] CCSID[1:3] CMVFP CMVFPC CMV8MCLK
Inputs Tim ed to C M V8MC LK
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
A separate H-MVIP interface consisting of twenty-one pins is for access to the channel associated signaling for all of the 2016 data channels. The CAS is time division multiplexed exactly the same way as the data channels and is synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame, the four CAS bits per channel are repeated with each data byte. The CAS H-MVIP interface can be used in parallel with the SBI Drop bus as an alternative method for accessing the CAS bits while data transfer occurs over the
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nt e
nt Te a
Twenty-one H-MVIP data signals, MVID[1:21] provide H-MVIP access for up to 2016 data channels. The H-MVIP mapping is fixed such that each group of four nearest neighbor T1 or E1 links make up the individual 8.192 Mbit/s H-MVIP signal. This mode is selected when the SYSOPT[1:0] bits in the Global Configuration register are set to H-MVIP.
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tm
The three ingress H-MVIP interfaces operate independently except that using any one of these forces the T1 or E1 framer to operate in synchronous mode, meaning that elastic stores are used.
in
er
In
When Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP ingress interface multiplexes up to 2016 channels from 84 T1s or 63 E1s, up to 2016 channel associated signaling (CAS) channels from 84 T1s or 63 E1s and common channel signaling (CCS) from up to 84 T1s or 63 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization.
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Tu
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da
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14
Se
Ingress System Interface
pt
em
MVID [1:21]
be
ELST Elastic Store
r,
T1/E1 FRM R Fram er: Fram e Alignment, Alarm Extraction
RJAT Digital Jitter Attenuator
04
RECEIVER
Figure 19
- Ingress Clock Slave
- H-MVIP
07
of the system side interface is global to TEMUX 84 and is selected through the SYSOPT[1:0] bits in the Global Configuration register at address 0x0002. The system interface options are H-MVIP, SBI bus and SBI bus with CAS or CCS HMVIP. The ingress H-MVIP interface is always a clock slave.
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3:
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AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
From DS3 Multiplexer or SONET/SDH mapper
143
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
All egress links extracted from the SBI bus can be timed from the source or from the TEMUX 84. When timing is from the source, the 1.544 Mbit/s, 2.048 Mbit/s, 34.368 Mbit/s or 44.736 Mbit/s internal clocks are slaved to the arrival rate of the data. For 34.368 Mbit/s or 44.736 Mbit/s data streams there is also the option of using timing link rate adjustments provided from the source and carried with the links over the SBI bus. A T1/E1 tributary may be transmitted at a rate different from that of the SBI bus if the tributary is looped timed, locked to the CTCLK input or locked to a selected recovered clock. In this case, the frame slip buffer (ELST) must be used to adapt the data rate. The 44.736 Mbit/s or 34.368 Mbit/s clock is synthesized from the 51.84 MHz or 44.928 MHz reference clock, CLK52M. Using either reference clock frequency, the 44.736 Mbit/s or 34.368 Mbit/s rate is generated by gapping the reference
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nt e
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The Extract Scaleable Bandwidth Interconnect block demaps up to 84 1.544 Mbit/s links, 63 2.048 Mbit/s links, three 44.736 Mbit/s links, three 34.386 Mbit/s links or an arbitrary bit rate from the SBI shared bus. The SBI bandwidth is evenly divided into three SPEs, each of which may carry a different payload type. The 1.544 Mbit/s links can be unframed or they can be T1 framed and channelized for insertion into the DS3 multiplex or SONET/SDH mapping. The 2.048 Mbit/s links can be unframed or they can be E1 framed and channelized for insertion into the SONET/SDH mapping or G.747 multiplexer. The 44.736 Mbit/s links can also be unframed for mapping into SONET/SDH. The 44.736 Mbit/s links and 34.368 Mbit/s links can be DS3/E3 unchannelized when the TEMUX 84 is used as a DS3/E3 framer. Finally, an arbitrary bandwidth signal may be carried for presentation on the Flexible Bandwidth Port. The SBI Bus Data Formats section provides the details of the mapping formats.
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tm
in
er
In
co
n
Tu
es
da
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14
9.29 Extract Scaleable Bandwidth Interconnect (EXSBI)
Se
When accessing the CAS or CCS signaling via the H-MVIP interface in parallel with the SBI interface a receive signaling elastic store is used to adapt any timing differences between the data interface and the CAS or CCS H-MVIP interface.
pt
em
be
A separate H-MVIP interface consisting of three signals is used to time division multiplex the common channel signaling (CCS) for all T1s and E1s and additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSID[1:3], is not multiplexed with any other pins. The CCSID[1:3] outputs is always available provided CMV8MCLK, CMVFPB and CMVFPC are active.The TS0ID output provides the contents of E1 TS0.
r,
20
04
07
:4
3:
SBI bus. This is selected when the SYSOPT[1:0] bits in the Global Configuration register are set to "SBI Interface with CAS or CCS H-MVIP Interface".
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
144
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
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The Insert Scaleable Bandwidth Interconnect block maps up to 84 1.544 Mbit/s links, 63 2.048 Mbit/s links, three 44.736 Mbit/s links, three 34.386 Mbit/s links or an arbitrary bit rate into the SBI shared bus. The SBI bandwidth is evenly divided into three SPEs, each of which may carry a different payload type. The 1.544 Mbit/s links can be unframed when sourced directly from the DS3 multiplexer or SONET/SDH mapper, or they can be T1 channelized when sourced by the T1 framers. The 2.048 Mbit/s links can be unframed when sourced directly from the SONET/SDH mapper or G.747 demultiplexer, or they can be E1 channelized when sourced by the E1 framers. The 44.736 Mbit/s links and 34.368 Mbit/s links can also be unframed when sourced directly from the DS3/E3 interfaces or from the DS3 mapper. The 44.736 Mbit/s links and 34.368 Mbit/s links can be unchannelized DS3/E3s when sourced from the DS3 or E3 framers. Finally, an arbitrary bandwidth signal that has been received Flexible Bandwidth Port may be output. The SBI Bus Data Formats section provides the details of the mapping formats.
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tm
in
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In
co
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Tu
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9.30 Insert Scaleable Bandwidth Interconnect (INSBI)
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Channelized T1s extracted from the SBI bus optionally have the channel associated signaling (CAS) bits explicitly defined and carried in parallel with the DS0s.
14
Se
pt
When the TEMUX 84 is the SBI egress clock master for a link, clocks are sourced from within the TEMUX 84. The data rate is set by the frequency of the CTCLK input, one of the three recovered clocks (RECVCLK1, RECVCLK2, or RECVCLK3) or the tributary receive clock if loop timed. Based on buffer fill levels, the EXSBI sends link rate adjustment commands to the link source indicating that it should send one additional or one fewer bytes of data during the next 500 S interval. Failure of the source to respond to these commands will ultimately result in overflows or underflows which can be configured to generate per link interrupts.
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07
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3:
clock in a fixed way. Timing adjustments are performed by adding or deleting four clocks over the 500 S period.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
145
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
SDPL SDV5 SDC1FP SREFCLK
9.31 Flexible Bandwidth Ports Three Flexible Bandwidth Ports are provided to supply arbitrary bandwidth signals to the SBI bus. Each port is associated with one SPE on the SBI bus and may carry up to the capacity of the SPE (48.96 Mbit/s). In the ingress direction, data is presented as a three wire interface: a clock of up to 51.84 MHz, bit serial data and an enable. No flow control is provided, so the average data rate must be less than 48.96 Mbit/s.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
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Channelized T1s inserted into the SBI bus optionally have the channel associated signaling (CAS) bits explicitly defined and carried in parallel with the DS0s or timeslots.
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The INSBI always sends valid link rate information across the SBI Drop bus, which contains both ClkRate(1:0) and Phase(3:0) field information. this gives an external device receiving data from the INSBI three methods of creating a recovered link clock: the ClkRate field, the Phase field, or just the rate of data flow across the SBI drop bus. INSBI does not generate the Phase field for DS3/E3 tribs.
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tm
in
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In
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Links inserted into the SBI bus can be synchronous to the SBI bus (by setting SYNCH_TRIB=1 in the INSBI Control RAM) or timed from the upstream data source via the sonet/sdh mapper, M13, or DS3/E3 framer. When SYNCH_TRIB is logic 0, the INSBI makes link rate adjustments by adding or deleting an extra byte of data over a 500 S interval based on buffer fill levels. Timing adjustments are detected by the receiving SBI interface by explicit signals in the SBI bus structure. When SYNCH_TRIB is logic 1, the tributary is "locked" in which no timing adjustments are allowed. The frame slip buffer (ELST) must be in the datapath in "locked" mode.
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be
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INSBI Ingress System Interface
20
T1/E1 FRM R Fram er: Fram e Alignment, Alarm Extraction
RJAT Digital Jitter Attenuator
04
SDDATA[7:0 ] SDDP
ELST Elastic Store
07
RECEIVER
:4
3:
From DS3 Multiplexer or SONET/SDH mapper
25
146
Figure 20
- Insert SBI
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
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The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The TEMUX 84 identification code is 183160CD hexadecimal.
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in
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In
9.32 JTAG Test Access Port
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3. 48.96 MHz < IFBWCLK < 51.5MHz: The length of the burst is dependent on how much the IFBWCLK frequency exceeds 48.96 MHz, but 256 bits can be buffered before an overflow occurs.
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2. IFBWCLK > 51.5 MHz: IFBWEN may only be high for up to eight consecutive cycles. The DS3 demapper satisfies this constraint when configured to use a 51.84 MHz clock.
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14
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1. IFBWCLK < 48.96 MHz: IFBWEN may be high indefinitely.
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em
The SBI bus is capable of transporting flexible bandwidth data up to 48.96 Mbit/s. The SBI interface contains a FIFO for absorbing data bursts in excess of this rate, but there is a limit to the length of the bursts. The limitations are dependent on the IFBWCLK frequency:
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r,
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04
9.31.1 Burst Lengths on Ingress Flexible Bandwidth Port
07
In the egress direction, a simple handshake controls the data flow. For each cycle that the EFBWDREQ[n] input is high, a bit may be output on the EFBWDAT[n] output. The data is supplied from the SBI bus FIFO, which will be kept half full through the SAJUST_REQ asserts as required.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
147
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0002 0x0003 0x0004 0x0005
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0x0008 0x0009 0x000A 0x000B
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0x0007
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0x0006
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Do wn lo
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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0x0001
tm
0x0000
Revision Global Reset Global Configuration SPE #1 Configuration SPE #2 Configuration SPE #3 Configuration Bus Configuration Global Performance Monitor Update Reference Clock Select Recovered Clock#1 Select Recovered Clock#2 Select Recovered Clock#3 Select
in
er
Address
In
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Table 9
- Register Memory Map Register
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Tu
On power up reset the TEMUX 84 defaults to 84 T1 framers multiplexed into the three M13 multiplexers using the DS3 M23 multiplex format. For proper operation some register configuration is necessary. System side access defaults to the SBI bus without any tributaries enabled which will leave the SBI Drop bus tristated. By default interrupts will not be enabled, automatic alarm generation is disabled, a dual rail DS3 LIU interface is expected and an external transmit reference clock is required.
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The Register Memory Map in Table 9 shows where the normal mode registers are accessed. The resulting register organization splits into sections: Master configuration registers, T1/E1 Framer registers, DS3 M13 multiplexing registers, SONET/SDH mapping registers and SBI registers.
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The Microprocessor Interface Block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the Microprocessor Interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the TEMUX 84.
04
07
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3:
148
9.33 Microprocessor Interface
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x000D 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x0021 0x0023 0x0040 0x0043 0x0042 0x0020 0x0022
Master Clock Monitor #1 Master Interrupt Source Master Interrupt Source T1E1 Master Interrupt Source SDH #1 Master Interrupt Source SDH #2 Master Interrupt Source SBI Master Interrupt Source SDH #3
Master Interrupt Source DS3/E3 #1 Master Interrupt Source MX12 #1 Master Interrupt Source DS2 #2 Master Interrupt Source MX12 #2 Master Interrupt Source DS2 #3 Master Interrupt Source DS3/E3 #3
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0x0044 0x0045 0x0046
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
Master Interrupt Source MX12 #3
Master SBIDET0 Collision Detect LSB Master SBIDET0 Collision Detect MSB Master SBIDET1 Collision Detect LSB Master SBIDET1 Collision Detect MSB T1/E1 Master Configuration
T1/E1 PRGD #1 Tributary Select T1/E1 PRGD #2 Tributary Select T1/E1 PRGD #3 Tributary Select T1/E1 PRGD #4 Tributary Select T1/E1 PRGD #5 Tributary Select
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Master Interrupt Source DS3/E3 #2
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Master Interrupt Source DS2 #1
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be
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04
07
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0x000C
Master H-MVIP Interface Configuration
3:
149
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052-0x0056 0x0057 0x0058 - 0x0062 0x0063 0x0064 0x0068 0x006A-0x006E 0x0069 0x006F
RJAT Indirect Status RJAT Indirect Channel Address Register RJAT Indirect Channel Data Register TJAT Indirect Status
TJAT Indirect Channel Data Register TJAT Programmable Corner Frequency Register RPCC-MVIP Indirect Channel Address Register RPCC-MVIP Configuration Bits RPCC-MVIP Interrupt Status RPCC-MVIP PRBS Error Insert Status RPCC-MVIP PRBS Error Insertion RPCC-MVIP Indirect Status/Time-slot Address RPCC-MVIP Indirect Channel Data Registers
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0x0070 - 0x007A 0x007C 0x0083
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0x007B
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0x0084 - 0x008E 0x008F - 0x0099 0x009A
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
RPCC-SBI Indirect Status/Time-slot Address RPCC-SBI Indirect Channel Data Registers
RPCC-SBI Indirect Channel Address Register
RPCC-SBI Configuration Bits RPCC-SBI Interrupt Status RPCC-SBI PRBS Error Insertion RPCC-SBI PRBS Error Insert Status RX-MVIP-ELST Idle Code RX-MVIP-ELST Slip Status RX-MVIP-ELST Slip Direction RX-MVIP-ELST Slip Interrupt Enable
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14
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pt
TJAT Indirect Channel Address Register
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be
RJAT Programmable Corner Frequency Register
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20
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07
:4
0x0047
T1/E1 PRGD #6 Tributary Select
3:
150
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x00A1 0x00A2 0x00A3 0x00A4 - 0x00AE 0x00AF - 0x00B9 0x00BA 0x00C0 0x00C1 0x00C2 0x00C4 - 0x00CE 0x00CF - 0x00D9 0x0DA 0x0100 0x0101 0x0102-0x0106 0x0107 0x0113 0x0118 0x0119 0x0108 - 0x0112 0x0114
RX-SBI-ELST Indirect Channel Address Register RX-SBI-ELST Idle Code RX-SBI-ELST Slip Status RX-SBI-ELST Slip Direction TX-ELST Indirect Status
TX-ELST Indirect Channel Address Register TX-ELST Slip Status
TPCC Indirect Status/Time-slot Address TPCC Indirect Channel Data Registers
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0x011E
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0x011A - 0x011D
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0x011F - 0x0129 0x0130 0x0131
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Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
TPCC Configuration TPCC Interrupt Status TPCC PRBS Error Insertion TPCC PRBS Error Insert Status RHDL Indirect Status RHDL Indirect Channel Address Register RHDL Indirect Channel Data Registers RHDL Interrupt Control RHDL Interrupt Status THDL Indirect Status THDL Indirect Channel Address Register
in
er
TPCC Indirect Channel Address Register
In
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TX-ELST Slip Interrupt Enable
Tu
TX-ELST Slip Direction
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TX-ELST Indirect Channel Data Register
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14
Se
pt
RX-SBI-ELST Slip Interrupt Enable
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be
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20
04
RX-SBI-ELST Indirect Channel Data Register
07
:4
0x00A0
RX-SBI-ELST Indirect Status
3:
151
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0137 - 0x0141 0x0150 0x0151 0x0152 - 0x0156 0x0157 0x0158 - 0x0162 0x0163 0x0168 0x0169 0x016A - 0x016F 0x0170 0x0171 0x0172 - 0x0186 0x0187 0x0188 - 0x0192 0x01C0 0x01C2 0x01C6 0x01C7 0x01C1 0x01C4
THDL Interrupt Status SIGX Indirect Status/Time-slot Address SIGX Indirect Channel Data Registers Change of Signaling Status SIGX Indirect Channel Address Register SIGX Configuration
Change of Signaling Status Interrupt Enable T1/E1 Transmitter Indirect Status T1/E1 Transmitter Indirect Channel Data Registers T1/E1 Framer Indirect Channel Address Register T1/E1 Framer Indirect Channel Data Registers T1/E1 Framer Interrupt Status T1/E1 Framer Configuration and Status T1/E1 Transmitter Indirect Channel Address T1/E1 Framer Indirect Status
of P
m
nt Te a
0x01D1
Co
0x01D0
nt e
by
0x01D2 0x01D3 0x01D4
ed
ad
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
SBI Master Reset / Bus Signal Monitor
SBI Master Configuration
SBI Bus Master Configuration DLL Configuration (SBI Bus) DLL Delay Tap Status (SBI Bus) DLL Control Status (SBI Bus) EXSBI Control EXSBI FIFO Underrun Interrupt Status EXSBI FIFO Overrun Interrupt Status EXSBI Tributary RAM Indirect Access Address EXSBI Tributary RAM Indirect Access Control
in
er
In
co
n
Tu
es
da
y,
14
Se
pt
em
be
r,
20
04
07
:4
0x0132 - 0x0136
THDL Indirect Channel Data Registers
3:
152
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x01D7 0x01D8 0x01D9 0x01DA 0x01DB 0x01DC 0x01DD 0x01DE 0x01DF 0x01E0 0x01E1 0x01E2 0x01E3 0x01E4 0x01E6 0x01E7 0x01EA 0x01F2 0x0200 0x0201 0x01E9 0x01F1
EXSBI SBI Parity Error Interrupt Status
EXSBI MIN_DEPTH for DS3 and E3 Register EXSBI E1 Threshold Register EXSBI E3 Threshold Register EXSBI Depth Check Interrupt Status INSBI Control Extract External ReSynch Interrupt Status INSBI FIFO Underrun Interrupt Status INSBI Tributary Indirect Access Address INSBI Tributary Control Indirect Access Data
of P
m
nt Te a
nt e
0x0200 - 0x2D5
Co
by
0x0202 0x0203 0x0204
ad
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
INSBI MIN_DEPTH for T1 and E1 Register
INSBI T1 Thresholds Register INSBI E1 Thresholds Register INSBI Depth Check Interrupt Status Insert External ReSynch Interrupt Status DS3/E3 Framer and M13 Multiplex #1 DS3 and E3 Master Reset DS3 and E3 Master Data Source
DS3 and E3 Master Unchannelized Interface Options DS3/E3 Master Transmit Line Options DS3/E3 Master Receive Line Options
in
er
INSBI Tributary Indirect Access Control
In
co
n
INSBI FIFO Overrun Interrupt Status
Tu
es
da
y,
14
Se
pt
EXSBI DS3 Threshold Register
em
be
EXSBI T1 Threshold Register
r,
20
04
EXSBI MIN_DEPTH for T1 and E1 Register
07
:4
0x01D6
EXSBI Tributary Control Indirect Access Data
3:
153
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0206 0x0207 0x0208 0x0209 0x020C 0x020D 0x020D 0x020E 0x020F 0x0210 0x0211 0x0214 0x0215 0x0216 0x0217 0x0218 0x021A 0x021B 0x0219
DS3 FRMR Status
of P
m
nt Te a
0x021D
Co
0x021C
nt e
by
0x021E 0x021F 0x0220
ed
ad
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
DS3/E3 PMON Framing Bit Error Event Count LSB
DS3/E3 PMON Framing Bit Error Event Count MSB
DS3 PMON Excessive Zeros LSB DS3 PMON Excessive Zeros MSB DS3/E3 PMON Parity Error Event Count LSB DS3/E3 PMON Parity Error Event Count MSB DS3 PMON Path Parity Error Event Count LSB DS3 PMON Path Parity Error Event Count MSB DS3/E3 PMON FEBE Event Count LSB DS3/E3 PMON FEBE Event Count MSB DS3/E3 TDPR Configuration
in
DS3/E3 PMON Line Code Violation Event Count MSB
er
In
DS3/E3 PMON Line Code Violation Event Count LSB
co
n
DS3/E3 PMON Interrupt Enable/Status
Tu
DS3/E3 PMON Performance Meters
es
da
y,
DS3 FRMR Interrupt Status
14
DS3 FRMR Additional Configuration (ACE=1)
Se
DS3 FRMR Interrupt Enable (ACE=0)
pt
DS3 FRMR Configuration
em
DS3 TRAN Diagnostic
be
r,
DS3 TRAN Configuration
20
E3 Data Link Control
04
DS2 Master Alarm Enable / DS3 Network Requirement Bit
07
:4
0x0205
DS3/E3 Master Alarm Enable
3:
154
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0222 0x0223 0x0224 0x0225 0x0228 0x0229 0x022A 0x022B 0x022C 0x022D 0x0230 0x0231 0x0232 0x0233 0x0234 0x0238 0x023A 0x023C 0x023D 0x023F 0x023E 0x0239 0x023B
DS3/E3 TDPR Lower Interrupt Threshold DS3/E3 TDPR Interrupt Enable DS3/E3 TDPR Transmit Data DS3/E3 RDLC Configuration DS3/E3 RDLC Status DS3/E3 RDLC Data DS3/E3 RDLC Interrupt Control DS3/E3 TDPR Interrupt Status/UDR Clear
PRGD Length PRGD Error Insertion
of P
m
nt Te a
nt e
Co
by
0x0240 0x0241 0x0242
ed
ad
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
PRGD Pattern Insertion #1 PRGD Pattern Insertion #2 PRGD Pattern Insertion #3 PRGD Pattern Insertion #4 PRGD Pattern Detector #1 PRGD Pattern Detector #2 PRGD Pattern Detector #3 PRGD Pattern Detector #4
MX23 Configuration MX23 Demux AIS Insert MX23 Mux AIS Insert
in
er
PRGD Tap
In
co
n
PRGD Interrupt Enable/Status
Tu
PRGD Control
es
DS3/E3 RDLC Secondary Address Match
da
DS3/E3 RDLC Primary Address Match
y,
14
Se
pt
em
be
r,
20
04
07
:4
0x0221
DS3/E3 TDPR Upper Transmit Threshold
3:
155
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0244 0x0245 0x0246 0x0248 0x0249 0x024A 0x024B 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 0x0256 0x0257 0x0258 0x025A 0x025C 0x0260 0x0270 0x0268 0x0259 0x025B
MX23 Loopback Request Insert MX23 Loopback Request Detect MX23 Loopback Request Interrupt FEAC XBOC Control FEAC XBOC Code FEAC RBOC Interrupt Status DS2 FRMR #1 Configuration DS2 FRMR #1 Interrupt Status
DS2 FRMR #1 FERR Count DS2 FRMR #1 PERR Count (MSB)
of P
m
nt Te a
nt e
Co
by
0x0278 0x0280 0x0288
ed
ad
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
MX12 #1Configuration and Control MX12 #1 Loopback Code Select MX12 #1 Mux/Demux AIS Insert MX12 #1 Loopback Activate MX12 #1 Loopback Interrupt DS2 FRMR #2 Registers MX12 #2 Registers DS2 FRMR #3 Registers MX12 #3 Registers DS2 FRMR #4 Registers MX12 #4 Registers
in
er
DS2 FRMR #1 PERR Count (LSB)
In
co
n
DS2 FRMR #1 Monitor Interrupt Enable/Status
Tu
DS2 FRMR #1 Status
es
da
DS2 FRMR #1 Interrupt Enable
y,
14
Se
pt
FEAC RBOC Configuration/Interrupt Enable
em
be
r,
20
04
07
:4
0x0243
MX23 Loopback Activate
3:
156
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0298 0x02A0 0x02A8 0x02B0 0x02B8 0x02C0 0x02C1 0x02C2 0x02C3 0x02C4 0x02C5 0x02C6 0x02C8 0x02C9 0x02CA 0x02CB 0x02D1 0x02D3 0x02D4 0x02D5 0x02D0 0x02D2
MX12 #5 Registers DS2 FRMR #6 Registers MX12 #6 Registers DS2 FRMR #7 Registers MX12 #7 Registers E3 FRMR Framing Options
E3 FRMR Maintenance Options E3 FRMR Framing Interrupt Enable E3 FRMR Maintenance Event Interrupt Enable E3 FRMR Maintenance Event Status E3 TRAN Framing Options E3 TRAN BIP-8 Error Mask E3 TRAN Status and Diagnostic Options E3 FRMR Framing Interrupt Indication and Status E3 FRMR Maintenance Event Interrupt Indication
of P
m
nt Te a
nt e
0x0300 - 0x03D5
Co
by
0x0400 - 0x04D5 0x0500, 0x0520, 0x0540, 0x0560, 0x0580, 0x05A0
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ar
tm
E3 TRAN Maintenance and Adaptation Options TTB Trail Trace Identifier Status TTB Indirect Address TTB Indirect Data
TTB Control
TTB Expected Payload Type Label TTB Payload Type Label Control/Status DS3/E3 Framer and M13 Multiplex #2 DS3/E3 Framer and M13 Multiplex #3 T1/E1 Pattern Generator and Detector Control
in
er
In
co
n
Tu
es
da
y,
14
Se
pt
em
be
r,
20
04
07
:4
0x0290
DS2 FRMR #5 Registers
3:
157
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0501, 0x0521, 0x0541, 0x0561, 0x0581, 0x05A1 0x0502, 0x0522, 0x0542, 0x0562, 0x0582, 0x05A2 0x0503, 0x0523, 0x0543, 0x0563, 0x0583, 0x05A3 0x0504, 0x0524, 0x0544, 0x0564, 0x0584, 0x05A4 0x0508, 0x0528, 0x0548, 0x0568, 0x0588, 0x05A8 0x0509, 0x0529, 0x0549, 0x0569, 0x0589, 0x05A9 0x050A, 0x052A, 0x054A, 0x056A, 0x058A, 0x05AA
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
0x050E, 0x052E, 0x054E, 0x056E, 0x058E, 0x05AE
Co
0x050D, 0x052D, 0x054D, 0x056D, 0x058D, 0x05AD
nt Te a
0x050C, 0x052C, 0x054C, 0x056C, 0x058C, 0x05AC
of P
0x050B, 0x052B, 0x054B, 0x056B, 0x058B, 0x05AB
m
nt e
by
ar
tm
T1/E1 Pattern Generator and Detector Pattern Insertion #4 T1/E1 Pattern Generator and Detector Pattern Detector #1 T1/E1 Pattern Generator and Detector Pattern Detector #2 T1/E1 Pattern Generator and Detector Pattern Detector #3
in
T1/E1 Pattern Generator and Detector Pattern Insertion #3
er
In
co
T1/E1 Pattern Generator and Detector Pattern Insertion #2
n
Tu
es
T1/E1 Pattern Generator and Detector Pattern Insertion #1
da
y,
14
T1/E1 Pattern Generator and Detector Error Insertion
Se
pt
em
T1/E1 Pattern Generator and Detector Tap
be
r,
20
T1/E1 Pattern Generator and Detector Length
04
07
T1/E1 Pattern Generator and Detector Interrupt Enable/Status
:4
3:
158
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x050F, 0x052F, 0x054F, 0x056F, 0x058F, 0x05AF 0x0510, 0x0530, 0x0550, 0x0570, 0x0590, 0x05B0 0x0511, 0x0531, 0x0551, 0x0571, 0x0591, 0x05B1 0x0512, 0x0532, 0x0552, 0x0572, 0x0592, 0x05B2 0x0513, 0x0533, 0x0553, 0x0533, 0x0593, 0x05B3 0x0514, 0x0534, 0x0554, 0x0574, 0x0594, 0x05B4 0x0515, 0x0535, 0x0555, 0x0575, 0x0595, 0x05B5
0x0702
Co
0x0701
nt e
0x0700
nt Te a
0x0517, 0x0537, 0x0557, 0x0577, 0x0597, 0x05B7
of P
0x0516, 0x0536, 0x0556, 0x0576, 0x0596, 0x05B6
m
by
0x0703 0x0704 0x0705
ed
ad
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
Receiver Controller Channel Indirect Address/Control Receiver Controller Channel Indirect Data Buffer
SONET/SDH Master Reset SONET/SDH Master Ingress Configuration SONET/SDH Master Egress Configuration SONET/SDH Master Ingress VTPP Configuration SONET/SDH Master Egress VTPP Configuration SONET/SDH Master RTOP Configuration
in
er
Receiver Controller P Access Status
In
co
n
Receiver Controller Configuration
Tu
es
da
Generator Controller Channel Indirect Data Buffer
y,
14
Generator Controller Channel Indirect Address/Control
Se
pt
em
Generator Controller P Access Status
be
r,
20
Generator Controller Configuration
04
07
T1/E1 Pattern Generator and Detector Pattern Detector #4
:4
3:
159
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0707 0x0708 0x0709 0x070A 0x070B 0x070C 0x070D 0x073C 0x073E 0x073F 0x740 - 0x077F 0x0740, 0x0742, 0x0744, 0x0746, 0x0748, 0x074A, 0x074C 0x0741, 0x0743, 0x0745, 0x0747, 0x0749, 0x074B, 0x074D
DLL Delay Tap Status (TelecomBus) Ingress VTPP #1
m
of P
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
0x074F
Co
0x074E
nt e
nt Te a
ar
tm
VTPP Ingress, TU #1 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Ingress, TU #1 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Ingress, TU #1 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Ingress, TU #1 in TUG2 #1 to TUG2 #7, AIS Interrupt
in
er
DLL Control Status (TelecomBus)
In
co
DLL Configuration (TelecomBus)
n
Tu
SONET/SDH Transmit Pointer Configuration #2 (LSB)
es
da
SONET/SDH Transmit Pointer Configuration #1 (MSB)
y,
14
SONET/SDH Telecom Bus Signal Monitor, Accumulation Trigger
Se
pt
SONET/SDH Master Loopback Control
em
SONET/SDH Master DS3/E3 Clock Generation Control
be
r,
SONET/SDH Master Tributary Auxiliary Remote Defect Indication Control
20
04
SONET/SDH Master Tributary Remote Defect Indication Control
07
:4
0x0706
SONET/SDH Master Tributary Alarm AIS Control
3:
160
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0760, 0x0762, 0x0764, 0x0766, 0x0768, 0x076A, 0x076C 0x0761, 0x0763, 0x0765, 0x0767, 0x0769, 0x076B, 0x076D 0x076E
by
0x0771, 0x0773, 0x0775, 0x0777, 0x0779, 0x077B, 0x077D 0x077E
nt e
nt Te a
0x0770, 0x0772, 0x0774, 0x0776, 0x0778, 0x077A, 0x077C
of P
0x076F
m
Co
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
ar
VTPP Ingress, TU #3 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Ingress, TU #3 in TUG2 #1 to TUG2 #7, AIS Interrupt VTPP Ingress, TU #4 in TUG2 #1 to TUG2 #7, Configuration and Status
tm
VTPP Ingress, TU #4 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Ingress, TU #4 in TUG2 #1 to TUG2 #7, LOP Interrupt
in
er
In
VTPP Ingress, TU #3 in TUG2 #1 to TUG2 #7, Alarm Status
co
n
Tu
es
VTPP Ingress, TU #3 in TUG2 #1 to TUG2 #7, Configuration and Status
da
y,
14
0x075F
VTPP Ingress, TU #2 in TUG2 #1 to TUG2 #7 AIS Interrupt
Se
pt
0x075E
VTPP Ingress, TU #2 in TUG2 #1 to TUG2 #7, LOP Interrupt
em
0x0751, 0x0753, 0x0755, 0x0757, 0x0759, 0x075B, 0x075D
be
r,
VTPP Ingress, TU #2 in TUG2 #1 to TUG2 #7, Alarm Status
20
04
0x0750, 0x0752, 0x0754, 0x0756, 0x0758, 0x075A, 0x075C
07
VTPP Ingress, TU #2 in TUG2 #1 to TUG2 #7, Configuration and Status
:4
3:
161
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x090E 0x090F
of P
m
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
0x0911, 0x0913, 0x0915, 0x0917, 0x0919, 0x091B, 0x091D
Co
0x0910, 0x0912, 0x0914, 0x0916, 0x0918, 0x091A, 0x091C
nt Te a
nt e
ed
by
ar
0x0901, 0x0903, 0x0905, 0x0907, 0x0909, 0x090B, 0x090D
tm
VTPP Egress, TU #1 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Egress, TU #1 in TUG2 #1 to TUG2 #7, AIS Interrupt VTPP Egress, TU #2 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Egress, TU #2 in TUG2 #1 to TUG2 #7, Alarm Status
in
VTPP Egress, TU #1 in TUG2 #1 to TUG2 #7, Alarm Status
er
In
0x0900, 0x0902, 0x0904, 0x0906, 0x0908, 0x090A, 0x090C
co
VTPP Egress, TU #1 in TUG2 #1 to TUG2 #7, Configuration and Status
n
Tu
es
0x0900 - 0x93F
Egress VTPP #1
da
0x0865
RTDM Indirect Ingress Tributary Data
y,
0x0864
RTDM Indirect Time Switch Internal Link Address
14
Se
0x0863
RTDM Indirect Time Switch Tributary RAM Status and Control
pt
0x0862
RTDM Time Switch Page Control
em
0x0860
Reserved
be
r,
0x0800 - 0x85E
RTDM Tributary Control
20
0x7C0 - 0x07FF
Ingress VTPP #3
04
0x780 - 0x07BF
Ingress VTPP #2
07
:4
0x077F
VTPP Ingress, TU #4 in TUG2 #1 to TUG2 #7, AIS Interrupt
3:
25
162
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x093F
nt Te a
m
0x093E
of P
0x0931, 0x0933, 0x0935, 0x0937, 0x0939, 0x093B, 0x093D
0x0980 - 0x9BF
Co
0x0940 - 0x97F
nt e
by
0x09C0 0x09C3
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ar
VTPP Egress, TU #4 in TUG2 #1 to TUG2 #7, Alarm Status
tm
VTPP Egress, TU #4 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Egress, TU #4 in TUG2 #1 to TUG2 #7, AIS Interrupt Egress VTPP #2 Egress VTPP #3 Byte Synchronous Mapping Control Register Byte Synchronous Mapping Tributary Indirect Access Address Register
in
0x0930, 0x0932, 0x0934, 0x0936, 0x0938, 0x093A, 0x093C
er
In
VTPP Egress, TU #4 in TUG2 #1 to TUG2 #7, Configuration and Status
co
n
Tu
0x092F
VTPP Egress, TU #3 in TUG2 #1 to TUG2 #7, AIS Interrupt
es
da
0x092E
VTPP Egress, TU #3 in TUG2 #1 to TUG2 #7, LOP Interrupt
y,
0x0921, 0x0923, 0x0925, 0x0927, 0x0929, 0x092B, 0x092D
14
Se
VTPP Egress, TU #3 in TUG2 #1 to TUG2 #7, Alarm Status
pt
em
0x0920, 0x0922, 0x0924, 0x0926, 0x0928, 0x092A, 0x092C
be
VTPP Egress, TU #3 in TUG2 #1 to TUG2 #7, Configuration and Status
r,
20
04
0x091F
VTPP Egress, TU #2 in TUG2 #1 to TUG2 #7 AIS Interrupt
07
:4
0x091E
VTPP Egress, TU #2 in TUG2 #1 to TUG2 #7, LOP Interrupt
3:
25
163
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x09E0 0x09E3 0x09E4 0x09E5 0x09E6 0x0x9EF 0x0A00 - 0x0AFD 0x0A00, 0x0A08, 0x0A10, 0x0A18, 0x0A20, 0x0A28, 0x0A30 0x0A01, 0x0A09, 0x0A11, 0x0A19, 0x0A21, 0x0A29, 0x0A31
Byte Synchronous Demapping Control Register
Byte Synchronous Demapping Tributary Control RAM Indirect Access Data Register
of P
nt Te a
m
by
Do wn lo
0x0A02, 0x0A0A, 0x0A12, 0x0A1A, 0x0A22, 0x0A2A, 0x0A32
Co
nt e
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
ar
tm
Byte Synchronous Demapping FIFO Control Register Receive Tributary Overhead Processor (RTOP) #1 RTOP, TU #1 in TUG2 #1 to TUG2 #7, Configuration
RTOP, TU #1 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
RTOP, TU #1 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
in
er
In
co
Byte Synchronous Demapping Tributary Mapping RAM Indirect Access Data Register
n
Tu
es
Byte Synchronous Demapping Tributary RAM Indirect Access Control Register
da
y,
Byte Synchronous Demapping Tributary RAM Indirect Access Address Register
14
Se
pt
0x09CA
Byte Synchronous Mapping E1 Thresholds Register
em
0x09C9
Byte Synchronous Mapping T1 Thresholds Register
be
r,
0x09C6
Byte Synchronous Mapping Tributary Control Indirect Access Data Register
20
04
0x09C5
Byte Synchronous Mapping Tributary Mapping Indirect Access Data Register
07
:4
0x09C4
Byte Synchronous Mapping Tributary Indirect Access Control Register
3:
164
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0A3B
nt Te a
m
0x0A3A
of P
0x0A39
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
0x0A40, 0x0A48, 0x0A50, 0x0A58, 0x0A60, 0x0A68, 0x0A70
Co
0x0A3D
nt e
0x0A3C
ed
by
ar
tm
RTOP, TU #1 in TUG2 #1 to TUG2 #7, PSLM Interrupt RTOP, TU #1 in TUG2 #1 to TUG2 #7, PSLU Interrupt RTOP, TU #1 in TUG2 #1 to TUG2 #7, RDI Interrupt RTOP, TU #1 in TUG2 #1 to TUG2 #7 RFI Interrupt
RTOP, TU #1 in TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration RTOP, TU #2 in TUG2 #1 to TUG2 #7, Configuration
in
0x0A38
RTOP, TU #1 in TUG2 #1 to TUG2 #7, COPSL Interrupt
er
0x0A07, 0x0A0F, 0x0A17, 0x0A1F, 0x0A27, 0x0A2F, 0x0A37
In
co
RTOP, TU #1 in TUG2 #2 to TUG2 #7, FEBE Error Count MSB
n
Tu
0x0A06, 0x0A0E, 0x0A16, 0x0A1E, 0x0A26, 0x0A2E, 0x0A36
es
da
RTOP, TU #1 in TUG2 #2 to TUG2 #7, FEBE Error Count LSB
y,
14
0x0A05, 0x0A0D, 0x0A15, 0x0A1D, 0x0A25, 0x0A2D, 0x0A35
Se
RTOP, TU #1 in TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB
pt
em
0x0A04, 0x0A0C, 0x0A14, 0x0A1C, 0x0A24, 0x0A2C, 0x0A34
be
r,
RTOP, TU #1 in TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB
20
04
0x0A03, 0x0A0B, 0x0A13, 0x0A1B, 0x0A23, 0x0A2B, 0x0A33
07
RTOP, TU #1 in TUG2 #1 to TUG2 #7, Accepted Path Signal Label
:4
3:
165
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0A79
Co
nt e
0x0A78
nt Te a
0x0A47, 0x0A4F, 0x0A57, 0x0A5F, 0x0A67, 0x0A6F, 0x0A77
of P
0x0A46, 0x0A4E, 0x0A56, 0x0A5E, 0x0A66, 0x0A6E, 0x0A76
m
by
ad
ed
0x0A7A 0x0A7B
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
RTOP, TU #2 in TUG2 #1 to TUG2 #7, FEBE Error Count LSB
RTOP, TU #2 in TUG2 #1 to TUG2 #7, FEBE Error Count MSB
RTOP, TU #2 in TUG2 #1 to TUG2 #7, COPSL Interrupt RTOP, TU #2 in TUG2 #1 to TUG2 #7, PSLM Interrupt RTOP, TU #2 in TUG2 #1 to TUG2 #7, PSLU Interrupt RTOP, TU #2 in TUG2 #1 to TUG2 #7, RDI Interrupt
in
er
0x0A45, 0x0A4D, 0x0A55, 0x0A5D, 0x0A65, 0x0A6D, 0x0A75
In
co
RTOP, TU #2 in TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB
n
Tu
0x0A44, 0x0A4C, 0x0A54, 0x0A5C, 0x0A64, 0x0A6C, 0x0A74
es
da
RTOP, TU #2 in TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB
y,
14
0x0A43, 0x0A4B, 0x0A53, 0x0A5B, 0x0A63, 0x0A6B, 0x0A73
Se
RTOP, TU #2 in TUG2 #1 to TUG2 #7, Accepted Path Signal Label
pt
em
0x0A42, 0x0A4A, 0x0A52, 0x0A5A, 0x0A62, 0x0A6A, 0x0A72
be
r,
RTOP, TU #2 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
20
04
0x0A41, 0x0A49, 0x0A51, 0x0A59, 0x0A61, 0x0A69, 0x0A71
07
RTOP, TU #2 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
:4
3:
25
166
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0A7D 0x0A80, 0x0A88, 0x0A90, 0x0A98, 0x0AA0, 0x0AA8, 0x0AB0 0x0A81, 0x0A89, 0x0A91, 0x0A99, 0x0AA1, 0x0AA9, 0x0AB1 0x0A82, 0x0A8A, 0x0A92, 0x0A9A, 0x0AA2, 0x0AAA, 0x0AB2 0x0A83, 0x0A8B, 0x0A93, 0x0A9B, 0x0AA3, 0x0AAB, 0x0AB3 0x0A84, 0x0A8C, 0x0A94, 0x0A9C, 0x0AA4, 0x0AAC, 0x0AB4 0x0A85, 0x0A8D, 0x0A95, 0x0A9D, 0x0AA5, 0x0AAD, 0x0AB5 0x0A86, 0x0A8E, 0x0A96, 0x0A9E, 0x0AA6, 0x0AAE, 0x0AB6 0x0A87, 0x0A8F, 0x0A97, 0x0A9F, 0x0AA7, 0x0AAF, 0x0AB7
of P
nt Te a
m
Co
nt e
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
ar
tm
RTOP, TU #3 in TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB
RTOP, TU #3 in TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB
TU #3 in TUG2 #1 to TUG2 #7, FEBE Error Count LSB
RTOP, TU #3 in TUG2 #1 to TUG2 #7, FEBE Error Count MSB
in
er
In
co
RTOP, TU #3 in TUG2 #1 to TUG2 #7, Accepted Path Signal Label
n
Tu
es
da
RTOP, TU #3 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
y,
14
Se
RTOP, TU #3 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
pt
em
be
r,
20
RTOP, TU #3 in TUG2 #1 to TUG2 #7, Configuration
04
RTOP, TU #2 in TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration
07
:4
0x0A7C
RTOP, TU #2 in TUG2 #1 to TUG2 #7, RFI Interrupt
3:
25
167
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0ABD 0x0AC0, 0x0AC8, 0x0AD0, 0x0AD8, 0x0AE0, 0x0AE8, 0x0AF0 0x0AC1, 0x0AC9, 0x0AD1, 0x0AD9, 0x0AE1, 0x0AE9, 0x0AF1 0x0AC2, 0x0ACA, 0x0AD2, 0x0ADA, 0x0AE2, 0x0AEA, 0x0AF2 0x0AC3, 0x0ACB, 0x0AD3, 0x0ADB, 0x0AE3, 0x0AEB, 0x0AF3
of P
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
0x0AC5, 0x0ACD, 0x0AD5, 0x0ADD, 0x0AE5, 0x0AED, 0x0AF5
Co
0x0AC4, 0x0ACC, 0x0AD4, 0x0ADC, 0x0AE4, 0x0AEC, 0x0AF4
nt Te a
m
nt e
ed
by
ar
tm
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Path Signal Label
RTOP, TU #4 in TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB
RTOP, TU #4 in TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB
in
er
In
co
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
n
Tu
es
da
y,
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Configuration
14
RTOP, TU #3 in TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration
Se
pt
0x0ABC
RTOP, TU #3 in TUG2 #1 to TUG2 #7, RFI Interrupt
em
0x0ABB
RTOP, TU #3 in TUG2 #1 to TUG2 #7, RDI Interrupt
be
r,
0x0ABA
RTOP, TU #3 in TUG2 #1 to TUG2 #7, PSLU Interrupt
20
04
0x0AB9
RTOP, TU #3 in TUG2 #1 to TUG2 #7, PSLM Interrupt
07
:4
0x0AB8
RTOP, TU #3 in TUG2 #1 to TUG2 #7, COPSL Interrupt
3:
168
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0D00 - 0x0D06 0x0D07
of P
nt Te a
m
0x0D0F
Co
nt e
0x0D08 - 0x0D0E
by
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
0x0D10 - 0x0D16
ar
0x0C00 - 0x0CFD
tm
Receive Tributary Overhead Processor (RTOP) #3 TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #1 Control
in
0x0B00 - 0x0BFD
Receive Tributary Overhead Processor (RTOP) #2
er
In
0x0AFD
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration
co
0x0AFC
RTOP, TU #4 in TUG2 #1 to TUG2 #7, RFI Interrupt
n
Tu
0x0AFB
RTOP, TU #4 in TUG2 #1 to TUG2 #7, RDI Interrupt
es
da
0x0AFA
RTOP, TU #4 in TUG2 #1 to TUG2 #7, PSLU Interrupt
y,
14
0x0AF9
RTOP, TU #4 in TUG2 #1 to TUG2 #7, PSLM Interrupt
Se
pt
0x0AF8
RTOP, TU #4 in TUG2 #1 to TUG2 #7, COPSL Interrupt
em
0x0AC7, 0x0ACF, 0x0AD7, 0x0ADF, 0x0AE7, 0x0AEF, 0x0AF7
be
r,
RTOP, TU #4 in TUG2 #1 to TUG2 #7, FEBE Error Count MSB
20
04
0x0AC6, 0x0ACE, 0x0AD6, 0x0ADE, 0x0AE6, 0x0AEE, 0x0AF6
07
RTOP, TU #4 in TUG2 #1 to TUG2 #7, FEBE Error Count LSB
:4
3:
25
169
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0D47
nt Te a
m
0x0D40 - 0x0D46
of P
0x0D3F
0x0D48 - 0x0D4E
nt e
ed
by
0x0D4F 0x0D50 - 0x0D56
Co
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ar
tm
TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control
in
0x0D38 - 0x0D3E
TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control
er
In
0x0D37
TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control
co
n
0x0D30 - 0x0D36
TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control
Tu
es
0x0D2F
TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control
da
y,
0x0D28 - 0x0D2E
TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control
14
Se
0x0D27
TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control
pt
em
0x0D20 - 0x0D26
TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control
be
r,
0x0D1F
TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control
20
04
0x0D18 - 0x0D1E
TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control
07
:4
0x0D17
TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control
3:
170
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0D62 0x0D63 0x0D68 0x0D69- 0x0D6E 0x0D70 - 0x0D76 0x0D78 - 0x0D7E 0x0D80
TRAP Indirect Datapath Tributary Data TRAP RDI Control TRAP Remote Parallel Alarm Port TUG2 #1 of TUG3 #1 Configuration
0x0D88 - 0x0D8E 0x0D8F
nt Te a
m
0x0D87
of P
0x0D81 - 0x0D86
nt e
ed
by
0x0D90 - 0x0D96 0x0D97
Co
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ar
tm
TTOP TU #1 in TUG2 #1 of TUG3 #1, Control
TTOP TU #1 in TUG2 #2 to TUG2 #7 of TUG3 #1, Control TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #1 BIP Diagnostic Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #1 BIP Diagnostic Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #1, BIP Diagnostic Control
in
TRAP Remote Parallel Alarm Port TUG2 #1 to TUG2 #7 of TUG3 #3 Configuration
er
In
co
TRAP Remote Parallel Alarm Port TUG2 #1 to TUG2 #7 of TUG3 #2 Configuration
n
Tu
TRAP Remote Parallel Alarm Port TUG2 #2 to TUG2 #7 of TUG3 #1 Configuration
es
da
y,
14
Se
pt
0x0D61
TRAP Indirect Remote Alarm Tributary Address
em
0x0D60
TRAP Indirect Remote Alarm Page Address
be
r,
0x0D5F
TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control
20
04
0x0D58 - 0x0D5E
TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control
07
:4
0x0D57
TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control
3:
171
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0DB8 - 0x0DBE 0x0DBF 0x0DC0 - 0x0DC6 0x0DC7
of P
0x0DD0 - 0x0DD6
Co
nt e
0x0DCF
nt Te a
0x0DC8 - 0x0DCE
m
by
ad
ed
0x0DD7 0x0DD8 - 0x0DDE
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ar
tm
TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #3, BIP Diagnostic Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #3, BIP Diagnostic Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #3, BIP Diagnostic Control TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control
in
TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control
er
In
TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control
co
n
Tu
0x0DB7
TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control
es
0x0DB0 - 0x0DB6
TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control
da
y,
0x0DAF
TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control
14
Se
0x0DA8 - 0x0DAE
TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control
pt
em
0x0DA7
TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control
be
r,
0x0DA0 - 0x0DA6
TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control
20
04
0x0D9F
TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #1, BIP Diagnostic Control
07
:4
0x0D98 - 0x0D9E
TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control
3:
172
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0E61 0x0E62 0x0E63 0x0E64 0x0E65 0x0E80 - 0x0E82 0x0E80 0x0E81 0x0E82 0x0E84 - 0x0E86 0x0E88 - 0x0E8A 0x0E8C - 0x0E8E 0x0E8C
TTMP Time Switch Page Control TTMP Indirect Egress Tributary Address TTMP Indirect Time Switch Internal Link Data TTMP Telecom Interface Configuration D3MD Control D3MD Interrupt Status D3MD Interrupt Enable D3MD #2 D3MD #3 D3MA #1 D3MA Control D3MA Interrupt Status D3MA Interrupt Enable D3MA #2 D3MA #3 RTTB #1 D3MD #1
0x0E8D
ad
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
0x0E8E 0x0E90 - 0x0E92 0x0E94 - 0x0E96 0x0F00 - 0x0F2B
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
TTMP Indirect Time Switch RAM Control and Status
es
da
y,
0x0E00 - 0x0E5E
TTMP Tributary Control
14
0x0DE7
TTOP Indirect Trail Trace Identifier Buffer Data
Se
0x0DE6
TTOP Indirect Trail Trace Identifier Buffer Address
pt
0x0DE5
TTOP Indirect Trail Trace Identifier Tributary Select
em
0x0DE4
TTOP Trail Trace Identifier Page Select
be
r,
0x0DE2
TTOP TUG3 #3 Control
20
0x0DE1
TTOP TUG3 #2 Control
04
0x0DE0
TTOP TUG3 #1 Control
07
:4
0x0DDF
TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #3, BIP Diagnostic Control
3:
173
25
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0x0F24 0x0F25 0x0F26 0x0F28 0x0F29 0x0F2A 0x0F2B 0x0F27
RTTB TU3 or TU #1 in TUG2 #1 to TUG2 #7, TIU Interrupt
of P
nt Te a
m
0x0F40 - 0x0F6B 0x0F80 - 0x0FAB
nt e
Co
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
0x1000
For all register accesses, CSB must be low.
ar
tm
RTTB TU #3 in TUG2 #1 to TUG2 #7, TIU Interrupt RTTB TU #4 in TUG2 #1 to TUG2 #7, TIU Interrupt
RTTB TIU Threshold RTTB Indirect Tributary Select RTTB Indirect Address Select RTTB Indirect Data Select RTTB #2 RTTB #3 Master Test
in
RTTB TU #2 in TUG2 #1 to TUG2 #7, TIU Interrupt
er
In
co
0x0F23
RTTB TU #4 in TUG2 #1 to TUG2 #7, TIM Interrupt
n
Tu
0x0F22
RTTB TU #3 in TUG2 #1 to TUG2 #7, TIM Interrupt
es
0x0F21
RTTB TU #2 in TUG2 #1 to TUG2 #7, TIM Interrupt
da
y,
0x0F20 + 0x40*N
RTTB TU3 or TU #1 in TUG2 #1 to TUG2 #7, TIM Interrupt
14
Se
0x0F18 to 0x0F1E
RTTB TU #4 in TUG2 #1 to TUG2 #7, Configuration and Status
pt
0x0F10H to 0x0F16
RTTB TU #3 in TUG2 #1 to TUG2 #7, Configuration and Status
em
be
r,
0x0F08 to 0x0F0E
RTTB TU #2 in TUG2 #1 to TUG2 #7, Configuration and Status
20
04
0x0F01 to 0x0F06
RTTB TU #1 in TUG2 #2 to TUG2 #7, Configuration and Status
07
:4
0x0F00
RTTB TU3 or TU #1 in TUG2 #1, Configuration and Status
3:
25
174
Address
Register
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
4. Writing into read-only normal mode register bit locations does not affect TEMUX 84 operation unless otherwise noted.
in
er
In
3. Writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted.
co
n
2. All configuration bits that can be written into can also be read back. This allows the processor controlling the TEMUX 84 to determine the programming state of the block.
Tu
es
da
1. Writing values into unused register bits typically has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bit must be written with logic 0. Reading back unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read.
y,
14
Se
pt
em
Notes on Normal Mode Register Bits:
be
The register descriptions are contained in a separate TEMUX 84 register description document.
r,
20
04
Normal mode registers are used to configure and monitor the operation of the TEMUX 84. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[12]) is low.
07
:4
3:
175
10
NORMAL MODE REGISTER DESCRIPTION
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
The TEMUX 84 contains test features for both production testing and board testing. Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the TEMUX 84. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[12]) is high.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
2. Writeable register bits are not initialized upon reset unless otherwise noted.
Tu
es
1. Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic one or a logic zero; hence unused bits should be masked off by software when read.
da
y,
14
Notes on Register Bits:
Se
pt
em
be
r,
20
04
07
:4
3:
176
11
TEST FEATURES DESCRIPTION
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W W R/W W R/W
PMCTST DBCTRL Reserved HIZDATA HIZIO
0 X 0 X 0
by
Reserved: These bits must be logic 0 for correct operation.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
Co
The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin while PMCTST is a logic 1. When the DBCTRL bit is set to logic 1, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the TEMUX 84 to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. When PMCTST is logic 0, the DBCTRL bit is ignored.
nt e
nt Te a
m
of P
DBCTRL:
ar
tm
The PMCTST bit is used to configure the TEMUX 84 for PMC's manufacturing tests. When PMCTST is set to logic 1, the TEMUX 84 microprocessor port becomes the test access port used to run the PMC "canned" manufacturing test vectors. The PMCTST bit can only be cleared by setting CSB to logic 1.
in
er
In
co
PMCTST:
n
Tu
This register is used to select TEMUX 84 test features. All bits, except for PMCTST, are reset to zero by a hardware reset of the TEMUX 84; a software reset of the TEMUX 84 does not affect the state of the bits in this register.
es
da
y,
14
Se
pt
em
be
r,
Bit 5
Unused
X
20
Bit 6
Unused
X
04
Bit 7
R/W
Reserved
0
07
Bit
Type
Function
Default
:4
3:
177
Register 0x1000: Master Test Register
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
The HIZIO bit controls the tri-state modes of the output pins of the TEMUX 84. While the HIZIO bit is a logic 1, all output pins of the TEMUX 84, except the data bus, are held in a high-impedance state. The microprocessor interface is still active.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
da
y,
14
Se
The HIZDATA bit controls the tri-state modes of the TEMUX 84. While the HIZIO bit is a logic 1, all output pins of the TEMUX 84, except the data bus, are held in a high-impedance state. While the HIZDATA bit is a logic 1, the data bus is held in a high-impedance state which inhibits microprocessor read cycles.
pt
em
be
r,
20
HIZDATA:
04
07
:4
3:
25
HIZIO:
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
178
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Table 10
- Instruction Register
EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Table 11 Length
Boundary Scan Boundary Scan
Tu
Identification Bypass Bypass Bypass
es
n
co
in
Boundary Scan Bypass
er
In
tm
- Identification Register
m
of P
ar
Version number Manufacturer's identification code Device identification
nt Te a
nt e
Part Number
Co
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
The boundary scan register is made up of 302 boundary scan cells, divided into input observation (IN_CELL), output (OUT_CELL) and bidirectional (IO_CELL) cells. These cells are detailed in the following pages. The first 32 cells form the
da
y,
000
001 010 011 100 101 110 111
32 bits 0x2 0x8316 0x0CD 0x283160CD
14
Instructions
Selected Register
Instruction Codes, IR[2:0]
Se
Length - 3 bits
pt
em
be
The TEMUX 84 JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section.
r,
20
04
07
:4
3:
179
11.1 JTAG Test Port
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Pin/ Enable
Bit #
Cell Type
Id Bit
Pin/ Enable
07
Table 12
- Boundary Scan Register
Bit #
:4
Cell Type
3:
ID code register and carry the code 283160CDH. The boundary scan chain order is presented in Table 12.
25
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Id Bit
SDC1FP_MVID_1 OEB_SDC1FP_MVID_1 SBIACT_MVID_2 OEB_SBIACT_MVID_2 SAJUST_REQ_MVID_3 OEB_SAJUST_REQ_ MVID_3 SDDATA_0_MVID_4 OEB_SDDATA_0_MVID_4 SDDATA_1_MVID_5 OEB_SDDATA_1_MVID_5 SDDATA_2_MVID_6 OEB_SDDATA_2_MVID_6 SDDATA_3_MVID_7 OEB_SDDATA_3_MVID_7 SDDATA_4_MVID_8 OEB_SDDATA_4_MVID_8 SDDATA_5_MVID_9
0 1 2 3 4 5
IO_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
OEB_D_3 D_4 OEB_D_4 D_5 OEB_D_5 D_6
20
04
151 152 153 154 155 156 OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
-
7 8 9 10 11 12
OUT_CELL OUT_CELL OUT_CELL
-
da
y,
6
OUT_CELL
-
OEB_D_6
14
Se
pt
em
be
r,
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178
OUT_CELL IO_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL
-
D_7 OEB_D_7 ALE RSTB A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 WRB RDB CSB
OUT_CELL
co
OUT_CELL
n
In er
OUT_CELL
tm
14
in
13
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
of P
ar
15
16 17 18 19 20 21 22 23 24 25 26 27
OEB_SDDATA_5_MVID_9
OEB_SDDATA_6_MVID_10 SDDATA_7_MVID_11 OEB_SDDATA_7_MVID_11
nt Te a
SDDATA_6_MVID_10
m
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
nt e
by
OEB_SDDP_MVID_12 SDPL_MVID_13 OEB_SDPL_MVID_13 SDV5_MVID_14 OEB_SDV5_MVID_14
Co
SDDP_MVID_12
ed
ad
Do wn lo
Tu
es
-
LAV5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
180
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
OEB_MVID_15 MVID_16 OEB_MVID_16 MVID_17 OEB_MVID_17 MVID_18 OEB_MVID_18 MVID_19 OEB_MVID_19 MVID_20 OEB_MVID_20 MVID_21 OEB_MVID_21 SREFCLK MVED_1 MVED_2 S77_MVED_3 SAC1FP_MVED_4 SADATA_0_MVED_5 SADATA_1_MVED_6 SADATA_2_MVED_7 SADATA_3_MVED_8
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
LAPL OEB_LAPL LADP OEB_LADP LADATA_0
07
180 181
:4
MVID_15
28
OUT_CELL
-
OEB_LAV5
179
3:
Bit
25
Pin/ Enable
Bit #
Cell Type
Id
Pin/ Enable
Bit #
Cell Type
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Id Bit -
OUT_CELL
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
04 20 be r,
182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
OEB_LADATA_0 LADATA_1
OEB_LADATA_1
es
Tu
-
IN_CELL
co
IN_CELL
n
-
In
IN_CELL
tm
46
in
45
er
IN_CELL
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
of P
ar
47 48 49 50
m
SADATA_4_MVED_9 SADATA_5_MVED_10 SADATA_6_MVED_11
nt Te a
51 52 53 54 55 56 57 58 59
nt e
SADP_MVED_13
Co
SADATA_7_MVED_12
by
SAPL_MVED_14 SAV5_MVED_15 SBIDET_0_MVED_16 SBIDET_1_MVED_17
ed
ad
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
da
y,
OEB_LADATA_2
LADATA_3 OEB_LADATA_3 LADATA_4
OEB_LADATA_4 LADATA_5 OEB_LADATA_5 LADATA_6 OEB_LADATA_6 LADATA_7 OEB_LADATA_7 LAOE/LATPL OEB_LAOE LAC1J1V1 OEB_LAC1J1V1 LAC1 CLK52M RADWEST RADWESTFP RADWESTCK RADEAST RADEASTFP
14
LADATA_2
Se
pt
em
181
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TS0ID OEB_TS0ID MVED_19 MVED_20 MVED_21 CCSID_1 OEB_CCSID_1 CCSID_2 OEB_CCSID_2 CCSID_3 OEB_CCSID_3 EFBWEN_1_CASID_1 OEB_EFBWEN_1_CASID_1 EFBWDAT_1_CASID_2 OEB_EFBWDAT_1_ CASID_2 CASID_3 OEB_CASID_3 CASID_4 OEB_CASID_4 CASID_5 OEB_CASID_5 CASID_6
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
LDAIS LDTPL LDV5 LDPL LDC1J1V1 LDDP LDDATA_0
07
212
:4
MVED_18
60
IN_CELL
-
RADEASTCK
211
3:
Bit
25
Pin/ Enable
Bit #
Cell Type
Id
Pin/ Enable
Bit #
Cell Type
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Id Bit -
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
04 20 be r, em pt
213 214 215 216 217 218 219 220 221 222 223 224 225 226
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
LDDATA_1
es
-
Tu
OUT_CELL
co
OUT_CELL
n
76
er
In
OUT_CELL
da
y,
LDDATA_3
LDDATA_4
LDDATA_5 LDDATA_6 LDDATA_7 L77
LREFCLK TNEG_TMFP_1 OEB_TNEG_TMFP_1 TCLK_1 OEB_TCLK_1 TPOS_TDAT_1 OEB_TPOS_TDAT_1 TICLK_1 RNEG_RLCV_1 RPOS_RDAT_1 RCLK_1 TNEG_TMFP_2 OEB_TNEG_TMFP_2 TCLK_2
14
LDDATA_2
Se
227 228 229 230 231 232 233 234 235 236 237 238 239 240
IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL
-
tm ar of P m
78 79 80 81 82 83 84 85 86 87 88 89
77
in
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
OEB_CASID_6
EFBWEN_2_CASID_8
ad
ed Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
OEB_EFBWEN_2_CASID_8 EFBWDAT_2_CASID_9 OEB_EFBWDAT_2_ CASID_9
Co
OEB_CASID_7
nt e
CASID_7
nt Te a
182
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
OEB_CASID_10 CASID_11 OEB_CASID_11 CASID_12 OEB_CASID_12 CASID_13 OEB_CASID_13 CASID_14 OEB_CASID_14 EFBWEN_3_CASID_15 OEB_EFBWEN_3_ CASID_15 EFBWDAT_3_CASID_16 OEB_EFBWDAT_3_ CASID_16 CASID_17 OEB_CASID_17 CASID_18 OEB_CASID_18
91 92 93 94 95 96 97 98 99 100 101
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
TPOS_TDAT_2 OEB_TPOS_TDAT_2 TICLK_2 RNEG_RLCV_2 RPOS_RDAT_2 RCLK_2
07
242
:4
CASID_10
90
OUT_CELL
-
OEB_TCLK_2
241
3:
Bit
25
Pin/ Enable
Bit #
Cell Type
Id
Pin/ Enable
Bit #
Cell Type
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Id Bit -
OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL
04 20
243 244 245 246 247 248 249 250 251 252
TNEG_TMFP_3 OEB_TNEG_TMFP_3
pt
em
be
r,
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
106
in
er
105
In
104
OUT_CELL
co
n
103
OUT_CELL
Tu
102
OUT_CELL
es
-
da
y,
OEB_TCLK_3 TPOS_TDAT_3
OEB_TPOS_TDAT_3 TICLK_3
14
TCLK_3
Se
253 254
OUT_CELL IN_CELL
-
-
-
RNEG_RLCV_3 RPOS_RDAT_3 RCLK_3 RGAPCLK_RSCLK_1 OEB_RGAPCLK_RSCLK_1 RDATO_1 OEB_RDATO_1 ROVRHD_1 OEB_ROVRHD_1 RFPO_RMFPO_1 OEB_RFPO_RMFPO_1 TFPO_TMFPO_ TGAPCLK_1
255 256 257 258 259 260 261 262 263 264 265 266
IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
OUT_CELL OUT_CELL OUT_CELL OUT_CELL
OEB_CASID_19 CASID_20 OEB_CASID_20 CASID_21
of P m
CASID_19
ar
tm
107 108
109 110 111 112 113 114 115
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL
CTCLK
CCSED_1
by
CCSED_2
Co
nt e
OEB_CASID_21
nt Te a
116
IN_CELL
-
OEB_TFPO_TMFPO_ TGAPCLK_1
267
OUT_CELL
-
ad
ed
CCSED_3 IFBWCLK_1_CASED_1
117 118
IN_CELL IN_CELL
-
TFPI_TMFPI_1 TDATI_1
268 269
IN_CELL IN_CELL
-
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
183
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
IFBWEN_1_CASED_3 EFBWCLK_1_CASED_4 EFBWDREQ_1_CASED_5 CASED_6 CASED_7 IFBWCLK_2_CASED_8 IFBWDAT_2_CASED_9 IFBWEN_2_CASED_10
120 121 122 123 124 125 126 127
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
-
OEB_RGAPCLK_RSCLK_2 RDATO_2 OEB_RDATO_2 ROVRHD_2 OEB_ROVRHD_2 RFPO_RMFPO_2 OEB_RFPO_RMFPO_2 TFPO_TMFPO_TGAPCLK_
07
271
:4
IFBWDAT_1_CASED_2
119
IN_CELL
-
RGAPCLK_RSCLK_2
270
3:
Bit
25
Pin/ Enable
Bit #
Cell Type
Id
Pin/ Enable
Bit #
Cell Type
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Id Bit 1 0 1 1 0 0 1 1 0
OUT_CELL OUT_CELL
04 20 r,
272 273 274 275 276 277 278
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
EFBWCLK_3_CASED_18 EFBWDREQ_3_CASED_19
135
in
er
IFBWEN_3_CASED_17
134
In
IFBWDAT_3_CASED_16
133
IN_CELL
co
IFBWCLK_3_CASED_15
132
IN_CELL
n
CASED_14
131
IN_CELL
Tu
CASED_13
130
IN_CELL
es
EFBWDREQ_2_CASED_12
129
IN_CELL
-
da
y,
EFBWCLK_2_CASED_11
128
IN_CELL
-
OEB_TFPO_TMFPO_ TGAPCLK_2
14
2
Se
pt
em
be
279
OUT_CELL
0
TFPI_TMFPI_2 TDATI_2 RGAPCLK_RSCLK_3 OEB_RGAPCLK_RSCLK_3
280 281 282 283 284 285 286 287 288 289 290
IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
0 0 0 1 1 0 1 0 0 0 1
-
-
RDATO_3 OEB_RDATO_3 ROVRHD_3 OEB_ROVRHD_3 RFPO_RMFPO_3 OEB_RFPO_RMFPO_3 TFPO_TMFPO_ TGAPCLK_3
IN_CELL
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
CASED_21 CMVFPB
of P m
CASED_20
CMVFPC
nt Te a
ar
tm
136 137 138 139
140
IN_CELL
-
OEB_TFPO_TMFPO_ TGAPCLK_3
291
OUT_CELL
1
OEB_INTB
Co
INTB
nt e
CMV8MCLK
141 142 143 144 145 146 147
IN_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
-
TFPI_TMFPI_3 TDATI_3 RECVCLK_3 OEB_RECVCLK_3 RECVCLK_2 OEB_RECVCLK_2 RECVCLK_1
292 293 294 295 296 297 298
IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
0 0 0 0 0 1 0
ed ad Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
D_0 OEB_D_0 D_1 OEB_D_1
184
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
OEB_D_2 D_3
149 150
OUT_CELL IO_CELL
-
XCLK_E1 XCLK_T1
07
300
:4
D_2
148
IO_CELL
-
OEB_RECVCLK_1
299
3:
Bit
25
Pin/ Enable
Bit #
Cell Type
Id
Pin/ Enable
Bit #
Cell Type
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Id Bit 1 0 0
OUT_CELL IN_CELL IN_CELL
Notes:
1. Register bit 301 is the first bit of the scan chain (closest to TDI). 2. Enable cell OEB_pinname, sets ball pinname to high-impedance when set high.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
da
y,
14
Se
pt
em
be
r,
20
04
301
185
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* * *
SPE #1, TUG-3 #1, DS3 #1 and MVID/MVED[1:7]
ed
by
Co
1.544Mbit/s SBI LINK #
nt e
Table 13 and Table 14 provide the equivalencies between the various multiplex and mapping formats. Alternately, the formats can be equated with the following formulae: = 7*(TU11-1) + TUG2 = 4*(DS2-1)+DS1 = 4*(MVED index - 7*(SPE-1) - 1) + DS1 = 7*(TU12-1) + TUG2 = 3*(DS2-1)+E1 = 4*(MVED index - 7*(SPE-1) - 1) + E1
2.048Mbit/s SBI LINK #
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
nt Te a
m
SPE #3, TUG-3 #3, DS3 #3 and MVID/MVED[15:21]
of P
SPE #2, TUG-3 #2, DS3 #2 and MVID/MVED[8:14]
ar
tm
in
The payload capacity is divided into three equal portions. Each of the following lists represents one set of equivalent tributaries:
er
In
co
The three DS3s are divided into seven DS2s, each of which is composed of either four 1.544 Mbit/s or three 2.048 Mbit/s tributaries.
n
Tu
The Telecom Bus indexing follows the conventions of the ITU-T multiplexing structure. The bandwidth is divided into three TUG-3s numbered 1 through 3, each of which is composed of seven TUG-2s numbered 1 through 7, each of which is composed of either three TU-12s numbered 1 through 3 or four TU-11s numbered 1 through 4.
es
da
y,
14
Se
The SBI Bus tributary designation uses two integers: the first represents the byte interleaved SPE number (range 1 to 3) and the second is the link index within the SPE (range 1 to 28).
pt
em
be
The TEMUX 84 is capable of transporting 84 1.544 Mbit/s (T1) or 63 2.048 Mbit/s (E1) tributaries. This section explains the correspondence between the indexing systems of the various mapping and multiplexing formats: SBI Bus, Telecom Bus, M13 and H-MVIP. The listed index systems are used throughout the document.
r,
20
04
07
12.1 Tributary Indexing
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12
OPERATION
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AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
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SBI Bus SPE, LINK 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 1,10 1,11 1,12 1,13 1,14 1,15 1,16 1,17 1,18 1,19 1,20 1,21 1,22 1,23 1,24 1,25 1,26 1,27 1,28 2,1 ...
Telecom Bus TUG-3, TUG-2, TU11 1,1,1 1,2,1 1,3,1 1,4,1 1,5,1 1,6,1 1,7,1 1,1,2 1,2,2 1,3,2 1,4,2 1,5,2 1,6,2 1,7,2 1,1,3 1,2,3 1,3,3 1,4,3 1,5,3 1,6,3 1,7,3 1,1,4 1,2,4 1,3,4 1,4,4 1,5,4 1,6,4 1,7,4 2,1,1 ...
M13 DS3, DS2, DS1 1,1,1 1,1,2 1,1,3 1,1,4 1,2,1 1,2,2 1,2,3 1,2,4 1,3,1 1,3,2 1,3,3 1,3,4 1,4,1 1,4,2 1,4,3 1,4,4 1,5,1 1,5,2 1,5,3 1,5,4 1,6,1 1,6,2 1,6,3 1,6,4 1,7,1 1,7,2 1,7,3 1,7,4 2,1,1 ...
H-MVIP port index, DS1 1,1 1,2 1,3 1,4 2,1 2,2 2,3 2,4 3,1 3,2 3,3 3,4 4,1 4,2 4,3 4,4 5,1 5,2 5,3 5,4 6,1 6,2 6,3 6,4 7,1 7,2 7,3 7,4 8,1 ...
ar
tm
in
er
In
co
n
Tu
es
da
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14
Se
pt
em
be
r,
20
04
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187
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Table 13
- Indexing for 1.544 Mbit/s Tributaries
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
The constraints given in the "19.44 MHz SBI Bus and 77.76 MHz Telecom Bus" section also apply when the system interface is H-MVIP. Except for the frequency tolerance allowed by the "TEMUX 84 Timing Characteristics" section, there are no constraints on CMV8MCLK and CMVFPB relative to other clocks.
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by
Co
nt e
12.2.1 H-MVIP and 77.76 MHz Telecom Bus
nt Te a
The following only applies when using the Telecom Bus. LREFCLK may be tied low when support is limited to DS3/E3 serial line interfaces.
m
Depending on the modes of operation utilized, some coordination between LREFCLK, SREFCLK, LAC1, LDC1J1V1, SDC1FP and SAC1FP is required. Specifically, tighter constraints must be respected when supporting transparent virtual tributaries (TVTs) or 77.76 MHz buses.
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ar
tm
in
12.2 Clock and Frame Synchronization Constraints
er
In
SBI Bus SPE, LINK 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 1,10 1,11 1,12 1,13 1,14 1,15 1,16 1,17 1,18 1,19 1,20 1,21 2,1 ...
Telecom Bus TUG-3, TUG-2, TU12 1,1,1 1,2,1 1,3,1 1,4,1 1,5,1 1,6,1 1,7,1 1,1,2 1,2,2 1,3,2 1,4,2 1,5,2 1,6,2 1,7,2 1,1,3 1,2,3 1,3,3 1,4,3 1,5,3 1,6,3 1,7,3 2,1,1 ...
M13 DS3, DS2, E1 1,1,1 1,1,2 1,1,3 1,2,1 1,2,2 1,2,3 1,3,1 1,3,2 1,3,3 1,4,1 1,4,2 1,4,3 1,5,1 1,5,2 1,5,3 1,6,1 1,6,2 1,6,3 1,7,1 1,7,2 1,7,3 2,1,1 ...
H-MVIP port index, E1 1,1 1,2 1,3 1,4 2,1 2,2 2,3 2,4 3,1 3,2 3,3 3,4 4,1 4,2 4,3 4,4 5,1 5,2 5,3 5,4 6,1 8,1 ...
co
n
Tu
es
da
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14
Se
pt
em
be
r,
20
04
07
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3:
188
25
Table 14
- Indexing for 2.048 Mbit/s Tributaries
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
* *
Table 15
nt Te a
m
The alignment below is also required when the TEMUX 84 is configured for transmux mode with a 77.76 MHz LREFCLK and SREFCLK. - 77.76 SBI and Telecom Bus Alignment Options
Clock Cycles LAC1 leads SDC1FP (n = 0, 1 , 2...) LSTM[1:0] 00 4n 4n + 3 4n + 2 4n + 1 01 4n + 1 4n 4n + 3 4n + 2 10 4n + 2 4n + 1 4n 4n + 3 11 4n + 3 4n + 2 4n + 1 4n
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SSTM[1:0] 00 01 10 11
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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For reliable operation, the STM-1s used within the SBI and Telecom buses must be aligned in time. To this end, one may manipulate the LSTM[1:0] and SSTM[1:0] register bits and the position of the LAC1 and SDC1FP pulses. Table 15 summarizes the combinations.
tm
in
er
In
The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the rising edge of SREFCLK.
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n
Tu
12.2.3 SBI and Telecom Buses Both 77.76 MHz
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If the Ingress VTPP is no bypassed, there is no restriction on the alignment of SDC1FP and LDC1J1V1.
da
y,
14
If the Ingress VTPP is bypassed, the LDC1J1V1 pulse must be precisely four SREFCLK cycles before the SDC1FP pulse.
Se
pt
If the Egress VTPP is not bypassed, the SAC1FP pulse must be 3n + 1 (where n = 0,1,2...) SREFCLK cycles before the LAC1 pulse.
em
*
be
r,
*
If the Egress VTPP is bypassed, the SAC1FP pulse must be precisely 13 SREFCLK cycles before the LAC1 pulse.
20
04
Restrictions on frame alignment pulses only exist when TVTs are supported:
07
The rising and falling edges of LREFCLK must be aligned with a tolerance of +/10ns to the corresponding edges of SREFCLK.
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189
12.2.2 SBI and Telecom Buses Both 19.44 MHz
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LSTM[1:0] SSTM[1:0] 00 01 10 11
12n 12n + 1 12n + 2 12n + 3
12n - 1 12n 12n + 1
Se
00
01
pt
em
Clock Cycles SAC1FP leads LAC1 (n = 0, 1 , 2...)
be
10 12n - 2 12n - 1 12n 12n + 1
r,
Table 16
- TVT Constraints for 77.76MHz
20
When TVTs are supported an additional constraint exists between SAC1FP and LAC1. Table 16 gives the permissible combinations.
04
07
(LSTM - SSTM) mod 4
= (Clock Cycles LAC1 leads SDC1FP) mod 4
:4
3:
As an alternate formulation, if SSTM[1:0] and LSTM[1:0] were converted to their decimal equivalents, one would have to satisfy the constraint:
25
12n + 1 12n + 2 12n + 3 12n
12n + 2
LSTM[1:0]
nt Te a
Table 17 Options
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- 19.44 MHz SBI to 77.76 MHz Telecom to Bus Alignment
LREFCLK Cycles LAC1 sampling edge leads SREFCLK rising edge 1 2 3 0
nt e
Co
00 01 10 11
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ed
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
As alternate formulation, if LSTM[1:0] was converted to its decimal equivalent, one would have to satisfy the constraint:
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For reliable operation, the STM-1s used within the Telecom bus must be aligned to the SREFCLK input. To this end, one may manipulate the LSTM[1:0] register bits and the position of the LAC1 pulses. Table 15 summarizes the combinations.
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tm
in
er
The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the rising edge of SREFCLK.
In
co
12.2.4 19.44 MHz SBI Bus and 77.76 MHz Telecom Bus
n
Tu
Note: Only the cases where SSTM equals LSTM have been validated.
es
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AM
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
12.2.5 77.76 MHz SBI Bus and 19.44 MHz Telecom Bus
The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the rising edge of SREFCLK. For reliable operation, the STM-1s used within the SBI bus must be aligned to LREFCLK. To this end, one may manipulate the SSTM[1:0] register bits and the position of the SDC1FP pulses. Table 15 summarizes the combinations. Table 18 Options - 77.76 MHz SBI to 19.44 MHz Telecom to Bus Alignment
SREFCLK Cycles SDC1FP sampling edge leads LREFCLK rising edge
12.3 SLC96
The following is a comprehensive discussion of the roles and responsbilities of TEMUX 84 and external logic in the support of the SLC96 standard, Bellcore TR-TSY-000008. While the TEMUX 84 handles most of the protocol functions, some external processing is required, especially of the datalink transported in the Fs bits.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
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nt e
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TVTs are not supported for this bus configuration.
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(SSTM + 1) mod 4 = Clock Cycles SDC1FP leads LREFCLK
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As alternate formulation, if SSTM[1:0] was converted to its decimal equivalent, one would have to satisfy the constraint:
tm
in
er
11
In
10
3
0
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01
2
n
00
1
Tu
es
da
SSTM[1:0]
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14
Se
pt
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20
04
07
:4
TVTs are not supported for this bus configuration.
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(LSTM + 1) mod 4 = Clock Cycles LAC1 leads SREFCLK
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12.3.2 Receive
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The T1 framer will determine frame alignment within 13ms if it is programmed to frame to SLC96 (i.e. ESF=0, FMS[1:0]=10) and is provided with valid SLC96 frame overhead. The framer is tolerant to the existence of the data link. Once in frame, only the Ft bits are used to determine loss of frame and for monitoring framing bit errors.
by
Co
nt e
nt Te a
Insertion of nine state signaling is straight forward. A sixteen bit encoding (i.e. ABCD) is used regardless of whether the signaling is inserted from the system interface or via register access through the T1/E1 Transmit Per-Channel Controller. The ABCD state is sampled every 24 frames. The "AB" values are inserted into the first superframe and the "CD" values are inserted into the second. Thus, if toggling A or B bits are required, it is sufficient that A C or B D, respectively.
m
of P
ar
tm
in
er
Because the F-bits are being sourced from the system interface, controlled frame slips must be avoided, if the TX-ELST is being used, to maintain superframe integrity. The T1/E1 transmit clock must be referenced to CTCLK. For SBI, CTCLK must be frequency locked to SREFCLK. Two alternate configurations for SBI avoid the need for the TX-ELST: the transmit clock is slaved to the data rate at the system interface or the TEMUX 84 acts as a timing master using the AJUST_REQ output to set the data rate.
In
co
n
Tu
es
da
y,
The TEMUX 84 can insert robbed bit signaling. For the TEMUX 84 to insert the signaling into the correct frames (6th and 12th), it must know the multiframe alignment consistent with the encoding of the F-bits. Therefore, it is imperative a multiframe indication is provided by the system inteface. For the SBI interface, the PPSSSSFR octets (those following V5) communicate multiframe alignment, signaling and the F-bits. The TRIB_TYP[1:0] bits of the EXSBI Tributary Control Indirect Access Data register should be set to "00" to configure the tributary to "Framed with CAS".
14
Se
pt
em
be
r,
20
While the TEMUX 84 supports transmission of AIS and the Yellow alarm, and supports signaling insertion, it is the responsibility of external logic to generate all F-bits. This means valid Ft and Fs bits as well as the datalink. To pass the F-bits transparently, the FDIS context bit must be set to logic 1 through the T1/E1 Transmitter Indirect Channel Data registers.
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192
12.3.1 Transmit
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PM8316 TEMUX 84
The datalink is not terminated within the TEMUX 84. Instead, it is provided on the SBI for external processing. Because the tributary may be subject to controlled frame slips, the external logic should be tolerant to the infrequent duplication or deletion of bits within the F-bit sequence. Signaling is terminated elegantly. The signaling for two consecutive superframes is captured as an aggregate presented as ABCD, with "CD" being the second set of A and B signaling bits. The ABCD bits are treated as cohesive state that is subject to debouncing (if enabled single bit errors will be filtered) and freezing. The four bits are available on the SBI Drop interface and through the SIGX Indirect Channel Data Register registers. A C is an indication that the A bit is toggling. B D is an indication that the B bit is toggling. (Note, the following signaling states are all equivalent; they all represent toggling A and B bits: 0110, 1100, 0011, 1001.) An interrupt on change of signaling will only occur if the collected ABCD state changes, but not just from toggling A or B bits.
M-subframe 7 M3
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M-subframe 5 M1 M-subframe 6 M2
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M-subframe 1 X 1 M-subframe 2 X 2 M-subframe 3 P 1 M-subframe 4 P 2
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F1 F1 F1 F1 F1 F1 F1
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84 bits
84 bits C1 C1 C1 C1 C1 C1 C1
tm
Figure 21
- DS3 Frame Structure
84 bits F2 F2 F2 F2 F2 F2 F2 84 bits C2 C2 C2 C2 C2 C2 C2 84 bits F3 F3 F3 F3 F3 F3 F3 84 bits C3 C3 C3 C3 C3 C3 C3 84 bits F4 F4 F4 F4 F4 F4 F4 84 bits
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Xx: X-Bit Channel
Transmit: The TEMUX 84 inserts the FERF signal on the X-bits. FERF generation is controlled by either the FERF bit of the DS3 TRAN Configuration register or by detection of OOF, RED, LOS and AIS, as configured by the TEMUX 84 Master DS3 Alarm Enable register.
Co
m
in
er
The TEMUX 84 provides support for both the C-bit parity and M23 DS3 framing formats. The DS3 frame format is shown in Figure 13.
In
co
n
12.4 DS3 Frame Format
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es
da
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14
Se
pt
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be
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04
07
:4
The presence of Yellow, Red, and AIS Carrier Fail Alarms is detected and integrated in accordance with the specifications defined in Bellcore TR-TSY000191.
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PM8316 TEMUX 84
Transmit: The TEMUX 84 generates the M-frame alignment signal (M1 = 0, M2 = 1, M3 = 0). Receive: The TEMUX 84 finds M-frame alignment by searching for the F-bits and the M-bits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. M-bit errors are counted in the DS3 PMON Framing Bit Error Event Count registers. When one or more M-bit errors are detected in 3 out of 4 consecutive M-frames, an out-of-frame defect is asserted (if MBDIS in the DS3 Framer Configuration register is a logic 0).
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Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
Cx: C-Bit Channels
Transmit: When configured for M23 applications, the C-bits used for stuffing indication. When configured for C-bit parity applications, the C-bit Parity ID bit is forced to logic 1. The second C-bit in M-subframe 1 is set to logic 1. The third C-
Co
Receive: The TEMUX 84 finds M-frame alignment by searching for the F-bits and the M-bits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. F-bit errors are counted in the DS3 PMON Framing Bit Error Event Count registers. An out-of frame defect is asserted if 3 F-bit errors out of 8 or 16 consecutive Fbits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration register).
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nt Te a
m
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Transmit: The TEMUX 84 generates the M-Subframe Alignment signal (F1=1, F2=0, F3=0, F4=1).
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tm
in
Fx: M-Subframe Alignment Signal
er
In
co
n
Tu
es
da
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14
Se
pt
Mx: M-Frame Alignment Signal
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Receive: The TEMUX 84 calculates the parity for the received payload. Errors are accumulated in the DS3 PMON Parity Error Event Count registers.
be
r,
20
Transmit: The TEMUX 84 calculates the parity for the payload data over the previous M-frame and inserts it into the P1 and P2 bit positions.
04
07
Px: P-Bit Channel
:4
3:
Receive: The TEMUX 84 monitors the state and detects changes in the state of the FERF signal on the X-bits.
25
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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4. If the INTB pin is still logic 0, then there are still interrupts to be serviced. Otherwise, all interrupts have been serviced. Wait for the next assertion of INTB
by
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nt e
3. Service the interrupt by reading the register containing the interrupt status bit that is asserted.
nt Te a
2. Read the bits of the second level Master Interrupt Source register to identify the interrupt source.
m
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1. Read the bits of the TEMUX 84 Master Interrupt Source register (0x0010) to identify which of the 14 interrupt registers (0x0011-0x001E) needs to be read to identify the interrupt. For example, a logic one read in the DS3E3INT register bit indicates that an interrupt identified in one of the three Master Interrupt Source DS3/E3 registers produced the interrupt.
ar
tm
in
er
The TEMUX 84 will assert INTB to logic 0 when a condition which is configured to produce an interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined below should be followed:
In
co
n
Tu
12.5 Servicing Interrupts
es
Receive: The CBITV register bit in the DS3 FRMR Status register is used to report the state of the C-bit parity ID bit, and hence whether a M23 or C-bit parity DS3 signal stream is being received. The FEAC channel on the third C-bit in Msubframe 1 is detected by the DS3 RBOC block. Path parity errors and detected FEBEs on the C-bits in M-subframes 3 and 4 are reported in the DS3 PMON Path Parity Error Event Count and FEBE Event Count registers respectively. The path maintenance datalink signal is extracted by theDS3 RDLC HDLC receiver (if enabled).
da
y,
14
Se
pt
em
be
bit in M-subframe 1 provides a far-end alarm and control (FEAC) signal. The FEAC channel is sourced by the DS3 XBOC block. The 3 C-bits in M-subframe 3 carry path parity information. The value of these 3 C-bits is the same as that of the P-bits. The 3 C-bits in M-subframe 4 are the FEBE bits. FEBE transmission is controlled by the DFEBE bit in the DS3 TRAN Diagnostic register and by the detection of receive framing bit and path parity errors. The 3 C-bits in Msubframe 5 contain the 28.2 kbit/s path maintenance datalink. These bits are inserted from the DS3 TDPR HDLC controller. The C-bits in M-subframes 2, 6, and 7 are unused and are set to logic 1.
r,
20
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
FEBE Table 20
nt Te a
Counter FER
m
- PMON Counter Saturation Limits (T1 mode) Format SF ESF SF ESF BER 1.6 x 10-3 6.4 x 10-2 1.28 x 10-1 cannot saturate
Co
ad
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
Below these 50% points, the relationship between the BER and the counter event count (averaged over many one second samples) is essentially linear.
nt e
CRCE
of P
ar
CRCE
cannot saturate
cannot saturate
tm
in
FER
4.0 X 10-3
er
In
Counter
BER
co
n
Table 19
- PMON Counter Saturation Limits (E1 mode)
Tu
The odds of any one of the T1/E1 counters saturating during a one second sampling interval go up as the bit error rate (BER) increases. At some point, the probability of counter saturation reaches 50%. This point varies, depending upon the framing format and the type of event being counted. The BER at which the probability of counter saturation reaches 50% is shown for various counters in Table 19 for E1 mode, and in Table 20 for T1 mode.
es
da
y,
14
Se
pt
An accumulation interval is initiated by writing to one of the PMON event counter register addresses or by writing to the Global PMON Update register. After initiating an accumulation interval, 3.5 recovered clock periods (RCLK for the DS3 PMON) must be allowed to elapse to permit the PMON counter values to be properly transferred before the PMON registers may be read.
em
be
r,
20
04
The counters in the DS3 PMON block has been sized as not to saturate if polled every second. The T1/E1 PMON event counters are of sufficient length so that the probability of counter saturation over a one second interval is very small (less than 0.001%).
07
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196
12.6 Using the Performance Monitoring Features
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PM8316 TEMUX 84
9 Bit Error Rate (x 10 -3 ) 8 7 6 5 4 3 2 1 0 0 50 Average Count Over Many 1 Second Intervals
co
n
Tu
100
es
da
y,
150
14
Se
pt
Figure 22
- FER Count vs. BER (E1 mode)
em
200
be
Figure 22 illustrates the expected count values for a range of Bit Error Ratios in E1 mode.
by
The bit error rate for E1 can be calculated from the one-second PMON CRCE count by the following equation:
8 log 1- CRCE 8000 8*256
ad
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Do wn lo
Bit Error Rate = 1 - 10
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
Co
Since the maximum number of CRC sub-multiframes that can occur in one second is 1000, the 10-bit FEBE and CRCE counters cannot saturate in one second. Despite this, there is not a linear relationship between BER and CRC-4 block errors due to the nature of the CRC-4 calculation. At BERs below 10-4, there tends to be no more than one bit error per sub-multiframe, so the number of CRC-4 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-4 error is often due to more than one bit error. Thus, the relationship between BER and CRCE count becomes non-linear above a 10-4 BER. This must be taken into account when using CRC-4 counts to determine the BER. Since FEBEs are indications of CRCEs at the far end, and are accumulated identically to CRCEs, the same explanation holds for the FEBE event counter.
nt e
nt Te a
m
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ar
tm
in
er
In
Framing Bit Error Count Per Second
r,
20
Above the 50% point, the relationship between BER and the average counter event count is highly non-linear due to the likelihood of counter saturation. The following figures show this relationship for various counters and framing formats. These graphs can be used to determine the BER, given the average event count. In general, if the BER is above 10-3, the average counter event count cannot be used to determine the BER without considering the statistical effect of occasional counter saturation.
250
04
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PM8316 TEMUX 84
1.00E-03 Bit Error Rate 1.00E-04
1.00E-06 1.00E-07 0 200 400
Figure 24
9
2 -
- FER Count vs. BER (T1 ESF mode)
Average Count Over Many 1 Second Intervals
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Figure 24 illustrates the expected count values for a range of Bit Error Ratios in T1 mode.
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150 200 250 Framing Bit Error Count Per Second
1.00E-02
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Since the maximum number of ESF superframes that can occur in one second is 333, the 9-bit BEE counter cannot saturate in one second in ESF framing format. Despite this, there is not a linear relationship between BER and BEE count, due to the nature of the CRC-6 calculation. At BERs below 10-4, there tends to be no
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Figure 23
- CRCE Count vs. BER (E1 mode)
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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PM8316 TEMUX 84
Bit Error Rate = 1 - 10
1.00E-02
Bit Error Rate
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- CRCE Count vs. BER (T1 ESF mode)
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The bit error rate for T1 ESF can be calculated from the one-second PMON CRCE count by the following equation:
CRCE
For T1 SF format, the CRCE and FER counts are identical, but the FER counter is smaller and should be ignored.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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more than one bit error per superframe, so the number of CRC-6 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-6 error is often due to more than one bit error. Thus, the relationship between BER and BEE count becomes nonlinear above a 10-4 BER. This must be taken into account when using ESF CRC6 counts to determine the BER.
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2 -
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0
200
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To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in the TDPR Upper Transmit Threshold and TDPR Lower Interrupt Threshold registers should be set to the desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR automatically begins the transmission of HDLC packets, even if no complete packets are in the FIFO. Transmission will continue until the current packet is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
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Upon reset of the TEMUX 84, the TDPR should be disabled by setting the EN bit in the TDPR Configuration Register to logic 0 (default value). An HDLC all-ones Idle signal will be sent while in this state. The TDPR is enabled by setting the EN bit to logic 1. The FIFOCLR bit should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit.
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It is important to note that access rate to the TDPR registers is limited by the rate of the internal DS3/E3 clock. Consecutive accesses to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than 1/8 that of the DS3 or E3 clock. This time is used by the high-speed system clock to sample the event, write the FIFO, and update the FIFO status. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the line clock) must be considered when determining the procedure used to read and write the TDPR registers.
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12.7 Using the Internal DS3 or E3 HDLC Transmitter
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400 600 800 Bit Error Event Count Per Second
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Average Count Over Many 1 Second Intervals
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Figure 26
- CRCE Count vs. BER (T1 SF mode)
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PM8316 TEMUX 84
transmitted and the number of bytes in the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all complete HDLC packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1, continuous flags will be sent. The TDPR can be used in a polled or interrupt driven mode for the transfer of data. In the polled mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status register to determine when to write to the TDPR Transmit Data register. In the interrupt driven mode, the processor controlling the TDPR uses the INTB output, the one of the TEMUX 84 Master Interrupt Source registers, and the TEMUX 84 TDPR Interrupt Status registers to identify TDPR interrupts which determine when writes can or must be done to the TDPR Transmit Data register.
3. If all bytes of the packet have been written to the Transmit Data register, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 4. If there are more bytes in the packet to be sent, then go to step 2. While performing steps 1 to 4, the processor should monitor for interrupts generated by the TDPR. When an interrupt is detected, the TDPR Interrupt Routine detailed in the following text should be followed immediately. The TDPR will force transmission of the packet information when the FIFO depth exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper Transmit Threshold register. Unless an error condition occurs, transmission will
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2. Write the data byte to the TDPR Transmit Data register.
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1. Wait for a complete packet to be transmitted. Once data is available to be transmitted, then go to step 2.
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The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 1 so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or a FIFO underrun. The following procedure should be followed to transmit HDLC packets:
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Interrupt Driven Mode:
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PM8316 TEMUX 84
TDPR Interrupt Routine:
1. Read the TDPR Interrupt Status register.
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4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written. When in this state, either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has since emptied out some of its data bytes and now has space available in its FIFO for more data.
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If the FIFO overflows on the packet currently being transmitted (packet is greater than 128 bytes long), OVRI is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied, and then flags are continuously sent until there is data to be transmitted. The FIFO is held in reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte of the next packet to be transmitted.
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3. If OVRI=1, then the FIFO has overflowed. The packet of which the last byte written into the FIFO belongs to, has been corrupted and must be retransmitted. Other packets in the FIFO are not affected. Either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit.
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2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To re-enable the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register should be written with any value.
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Upon assertion of INTB, the source of the interrupt must first be identified by reading the TEMUX 84 Master Interrupt Source register (0020H) followed by reading one of the second level master interrupt source registers T1E1INT1, T1E1INT2, T1E1INT3, T1E1INT4 or DS3INT. Once the source of the interrupt has been identified as the TDPR in use, then the following procedure should be carried out:
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not stop until the last byte of all complete packets is transmitted and the FIFO depth is at or below the threshold limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns and underruns.
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PM8316 TEMUX 84
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If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the data into the TDPR Transmit Data register. Go to step 6. If more data bytes are to be transmitted in the packet, then go to
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data into the TDPR Transmit Data register. Go to step 6.
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If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4 or 5 depending on implementation preference.
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2.
Read the TDPR Interrupt Status register.
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Wait until data is available to be transmitted, then go to step 2.
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The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. The following procedure should be followed to transmit HDLC packets:
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Polling Mode:
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If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lowerthreshold state earlier, but has since been refilled to a level above the lowerthreshold level.
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5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If there is more data to transmit, then it should be written to the TDPR Transmit Data register before an underrun occurs. If there is no more data to transmit, then an EOM should be set at the end of the last packet byte. Flags will then be transmitted once the last packet has been transmitted.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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When the last byte of a properly terminated packet is received, an interrupt is generated. While the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-of-packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC Status register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit
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After the RDLC Interrupt Control register has been written, the RDLC can be enabled at any time by setting the EN bit in the RDLC Configuration register to logic 1. When the RDLC is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written into the FIFO buffer. This is done to provide alignment of link up status with the data read from the FIFO. When an abort character is received, another dummy byte and link down status is written into the FIFO. This is done to provide alignment of link down status with the data read from the FIFO. It is up to the controlling processor to check the COLS bit in the RDLC Status register for a change in the link status. If the COLS bit is set to logic 1, the FIFO must be emptied to determine the current link status. The first flag and abort status encoded in the PBS bits is used to set and clear a Link Active software flag.
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On power up of the system, the RDLC should be disabled by setting the EN bit in the Configuration Register to logic 0 (default state). The RDLC Interrupt Control register should then be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be continuously polled to check the interrupt status (INTR) bit.
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It is important to note that the access rate to the RDLC registers is limited by the rate of the internal DS3 or E3 clock. Consecutive accesses to the RDLC Status and RDLC Data registers should be accessed at a rate no faster than 1/10 that of the selected RDLC high-speed system clock. This time is used by the highspeed system clock to sample the event and update the FIFO status. Instantaneous variations in the DS3 or E3 frequencies (e.g. jitter in the receive line clock) must be considered when determining the procedure used to read RDLC registers.
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12.8 Using the Internal DS3 or E3 Data Link Receiver
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If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1.
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PM8316 TEMUX 84
4.
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If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. If COLS = 1, then set the EMPTY FIFO software flag.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. Read the RDLC Data register. Read the RDLC Status register.
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If COLS = 1, then set the EMPTY FIFO software flag.
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If OVR = 1, then discard the last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost.
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Read the RDLC Status register. The INTR bit should be logic 1.
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In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of the TEMUX 84 is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the TEMUX 84 Master Interrupt Source register followed by one of the second level master interrupt source registers to identify one of the 3 HDLC receivers as the interrupt source. Once it has identified that the RDLC has generated the interrupt, it processes the data in the following order:
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The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the polled mode, the processor controlling the RDLC must periodically read the RDLC Status register to determine when to read the RDLC Data register. In the interrupt driven mode, the processor controlling the RDLC uses the TEMUX 84 INTB output and the TEMUX 84 Master Interrupt Source registers to determine when to read the RDLC Data register.
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When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt.
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will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits.
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PM8316 TEMUX 84
11.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt.
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The link state is typically a local software variable. The link state is inactive if the RDLC is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. The link state is active if the RDLC is receiving flags or data.
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If FE = 0 and INTR = 1 or FE = 0 and EMPTY FIFO = 1, go to step 5 else clear the EMPTY FIFO software flag and leave this interrupt service routine to wait for the next interrupt.
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If PBS[2:0] = 000, store the packet data.
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If PBS[2:0] = 1XX, discard the data byte read in step 5, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet.
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If PBS[2:0] = 010, discard the data byte read in step 5 and clear the LINK ACTIVE software flag.
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If PBS[2:0] = 001, discard data byte read in step 5 and set the LINK ACTIVE software flag.
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10.
Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data.
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9.
If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will be delayed until the FIFO fill level is exceeded.
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Sequence 0 1 1 1 1 1
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FF F D D D D F D D D D D D D D DD A FF F F DD D D FF 2 3 45 6 7
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Figure 28
- Example Multi-Packet Operational Sequence
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Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match.
- flag sequence (01111110) - abort sequence (01111111) - packet data bytes - active high interrupt output - internal FIFO empty status - state of the LINK ACTIVE software flag
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CONTROL
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data bytes received and transferred to the FIFO Buffer
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Address (high)
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Figure 27
- Typical Data Frame
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
12.9 Using the Internal T1/E1 Data Link Receiver A time-sliced HDLC receiver processes the data links extracted from the tributaries. Receive packets are queued in a dedicated 128 byte FIFO for each tributary. The reading of the FIFOs by an external microprocessor is usually done in response to an interrupt, but polling is also supported. On power up of the system, the receiver defaults to a disabled state. One must use the RHDL Indirect Channel Data registers to program each tributary. The configuration of each tributary is independent of all others. The RHDL Interrupt Control register should then be initialized to enable the INTB output and to select
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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At points 4 or 7 an abort character is detected, a dummy byte is written into the FIFO, and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. The LINK ACTIVE software flag is cleared.
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At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed.
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At points 2 and 6 the last byte of a packet is detected and interrupt goes high. When the interrupt is detected by the processor, it reads the data and status registers until the FIFO becomes empty. The interrupt is removed as soon as the RDLC Status register is read, since the FIFO fill level of 8 bytes has not been exceeded. It is possible to store many packets in the FIFO and empty the FIFO when the FIFO fill level is exceeded. In either case the processor should use this interrupt to count the number of packets written into the FIFO. The packet count or a software time-out can be used as a signal to empty the FIFO.
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At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte is written in the FIFO, FE goes low, and an interrupt goes active. When the interrupt is detected by the processor it reads the dummy byte, the FIFO becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software flag is set to logic 1.
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Figure 28 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link relative the input data sequence. The cause of each interrupt and the processing required at each point is described in the following paragraphs. The actual interrupt signal, INTB, is active low and will be the inverse of the INT signal shown in Figure 28. Also in this example, the programmable fill level set point is set at 8 bytes by writing this value into the INTC[6:0] bits of the RDLC Interrupt Control register.
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When the receiver is first enabled to delineate packets, it will assume the link is idle and immediately begin searching for flags. No bytes will be written into the FIFO until a flag is recognized. This is also true after an abort is detected. If packet delineation is disabled, all bytes are written raw into the FIFO. When the last byte of a properly terminated packet is received, an interrupt is generated. While the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-of-packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC Status register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits. When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt. The T1/E1 Receive HDLC processor (RHDL) can be used in a polled or interrupt driven mode for the transfer of packet data. In the polled mode, the processor controlling the RHDL must periodically read the RHDL Interrupt Status #1 register to determine if any tributaries need processing. In the interrupt driven mode, the processor controlling the RHDL uses the TEMUX 84 INTB output and the TEMUX 84 Master Interrupt Source registers to determine when to service the RHDL. In the case of interrupt driven data transfer from the RHDL to the processor, the INTB output of the TEMUX 84 is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the TEMUX 84 Master Interrupt Source register followed by the Master Interrupt Source T1E1 register to determine if RHDL is the interrupt source. Once it has identified that the RHDL has generated the interrupt, it processes the data in the following order: 1. Read the RHDL Interrupt Status #1 register. The value returned will indicate if any of RHDL Interrupt Status #2 through #11 should be read. Any bits returned as a logic 1 will indicate the associated tributary needs servicing. The bits in the RHDL Interrupt Status registers are write-one-to-clear, so the value read should be written back. Repeat steps 2 through 8 for each tributary with an INT bit set.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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the FIFO buffer fill level at which an interrupt will be generated. The FIFO threshold is a global setting optimized for a particular system by trading off minimizing the number of interrupts against avoiding FIFO overflows.
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
12.10 Using the Internal T1/E1 Data Link Transmitter A time-sliced HDLC transmitter (THDL) formats the data links inserted into the T1/E1 tributaries. Raw packets are written by an external microprocessor to a dedicated 128 byte FIFO for each tributary. The HDLC transmitter reads the FIFO once a complete packet is written or when a specified FIFO fill threshold is passed. Also, Performance Reporting Messages (PRMs) may be transmitted autonomously once a second. The transmitter takes care of bit stuffing and insertion of the CRC protection and flags.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Co
nt e
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If the RHDL data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt.
m
of P
ar
8. If FE = 0, go to step 3 else service the next tributary or exit this interrupt service routine to wait for the next interrupt.
tm
in
If PBS[2:0] = 000, store the packet data.
er
In
If PBS[2:0] = 1XX, store the last byte of the packet and check the PBS[1:0] bits for CRC or non-integer-byte errors before deciding whether or not to keep the packet.
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n
Tu
If PBS[2:0] = 010, an abort has occur so discard the data byte read in step 5.
es
da
7. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data.
y,
14
6. If OVR = 1, then discard the last frame and go to step 2. Overrun causes a reset of FIFO pointers and the loss of 128 bytes. Because an overflow likely occurred in the midst of a packet, discard all byte up to the next end-of-packet read.
Se
pt
em
be
5. Read the HDLC data byte from the RHDL Indirect Channel Data #1 register (0x011A).
r,
20
4. Read RHDL Indirect Channel Data #2 register (0x011B) until CBUSY is returned as logic 0. Store the last FE, OVR, PKIN and PBS[2:0] bits read.
04
07
3. Write the RHDL Indirect Status with 0x40 to initiate an indirect read.
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2. Write the RHDL Indirect Channel Address with the tributary index and set the FACCESS bit to logic 1.
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210
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
The T1/E1 Transmit HDLC processor (THDL) can be used in a polled or interrupt driven mode for the transfer of packet data. Minimum packet size for THDL is 2 bytes. In the polled mode, the processor controlling the THDL must periodically read the THDL Interrupt Status #1 register to determine if there's been a change in FIFO status. In the interrupt driven mode, the processor controlling the THDL uses the TEMUX 84 INTB output and the TEMUX 84 Master Interrupt Source registers to determine when to service the THDL. In the case of interrupt driven data transfer from the processor to THDL, the INTB output of the TEMUX 84 is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the TEMUX 84 Master Interrupt Source register followed by the Master Interrupt Source T1E1 register to determine if HDLC Transmitter is the interrupt source. Once it has identified that the THDL has generated the interrupt, it processes the data in the following order: 1. Read the THDL Interrupt Status #1 register. The value returned will indicate if any of THDL Interrupt Status #2 through #11 should be read. Any bits returned as a logic 1 will indicate the associated tributary needs servicing. The bits in the THDL Interrupt Status registers are write-one-to-clear, so the value read should be written back. Repeat steps 2 through 8 for each tributary with an INT bit set.
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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2. Write the THDL Indirect Channel Address with the tributary index and set the FACCESS bit to logic 1.
Co
nt e
nt Te a
m
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ar
tm
in
er
In
co
n
Tu
es
da
y,
FIFO thresholds must be set to avoid overflows and underflows, which result in lost data and an abort sequence. The actual thresholds depend on operating system latencies and algorithms used to write the packets. The Upper Transmit Threshold value determines how many bytes must be written before transmission of an incomplete packet starts. It should be set at a value large enough to ensure an underflow does not occur before the complete packet is written under worst case conditions, such as excessive interrupt servicing. Note that complete packets are always transmitted regardless of the Upper Transmit Threshold value. A large Upper Transmit Threshold value may result in FIFO overflows if large packets are being written. To avoid overflows, it is recommended writes only resume after the Lower Interrupt Threshold is reached.
14
Se
pt
em
be
r,
20
04
07
By default, the HDLC transmitter operates in a clear channel mode in which the contents of the FIFO are transmitted verbatim without bit stuffing or CRC. If the FIFO becomes empty, flags will be transmitted. To enable the HDLC features, the DELIN context bit must be set via the THDL Indirect Channel Data registers.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
211
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
The configuration of the 84 T1/E1 framers is stored in context RAMs. These RAMs are initialized to all zeros upon release of reset. This effectively places the framers in T1 SF mode with frame slip buffers and jitter attenuators in both the ingress and egress paths. All trunk conditioning and alarm generation defaults to disabled.
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by
Co
nt e
12.11.1
Initialization
nt Te a
12.11 Using the Time-Sliced T1/E1 Transceivers
m
c. Write a byte to the first THDL Indirect Channel Data Register (0x0133). This initiates the indirect write.
of P
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b. If the byte is the last of a packet, write a logic 1 to the EOM bit position of the second THDL Indirect Channel Data Register (0x0134).
tm
in
er
a. Read the THDL Indirect Status register (0x0130) until CBUSY is returned as logic 0.
In
co
8. A logic 1 LFILLI indicates the FIFO level has dropped below a programmed threshold or has become empty. Packet data may be written. If EMPTY is logic 1, 128 bytes may be written. If EMPTY is logic 0, 128 minus the LINT[6:0] value bytes may be written. Write the THDL Indirect Status register (0x0130) with 0x00 to configure indirect writes. Also, the EOM bit should be initialized to zero and need not be written for each byte except the last of the packet. For each byte, repeat the following:
n
Tu
es
da
y,
14
Se
7. A logic 1 UDRI indicates the FIFO for the tributary has underrun, a packet has been corrupted and an abort has been sent. The entire contents of the current packet should be written again to the FIFO.
pt
em
be
6. A logic 1 OVRI indicates the FIFO for the tributary has overflowed and a packet has been corrupted. The entire contents of the current packet should be written again to the FIFO.
r,
20
04
5. Read the THDL Indirect Channel Data #2 register (0x0133).
07
4. Read the THDL Indirect Status register until CBUSY is returned as logic 0.
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3. Write the THDL Indirect Status register (0x0130) with 0x40 to initiate an indirect read.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
212
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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nt e
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tm
in
er
In
1. The order of transmission of the bits is LSB (Bit 1) to MSB (Bit 8).
co
n
Notes:
Tu
Octet No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
es
da
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G3 FE G3 FE G3 FE G3 FE
LV SE LV SE LV SE LV SE
G5 G2 G5 G2 G5 G2 G5 G2
be
r,
SL Nm SL Nm SL Nm SL Nm
20
C/R
14
Se
pt
em
04
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4 FLAG SAPI TEI CONTROL G4 U1 U2 LB G1 R G4 U1 U2 LB G1 R G4 U1 U2 LB G1 R G4 U1 U2 LB G1 R FCS FCS FLAG
Bit 3
Bit 2
Bit 1 EA EA G6 NI G6 NI G6 NI G6 NI
07
:4
Table 21
- Performance Report Message Structure and contents
3:
26
213
12.12 T1 Automatic Performance Report Format
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
3 4 5,6 7,8 9,10 11,12 13,14 15
00000001 00000011 Variable Variable Variable Variable Variable 01111110
TEI=0,EA=1
Unacknowledged Frame Data for Previous Second(T'-1)
CRC16 Frame Check Sequence Closing LAPD flag
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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in
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In
co
n
Tu
es
da
Data for earlier Second(T'-3)
y,
Data for earlier Second(T'-2)
14
Se
Data for latest second (T')
pt
em
be
r,
00111010
From carrier: SAPI=14,C/R=1,EA=0
20
2
00111000
From CI:
SAPI=14, C/R=0, EA=0
04
1
01111110
Opening LAPD Flag
07
Octet No.
Octet Contents
Interpretation
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Table 22
- Performance Report Message Structure Notes
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
G2=1 G3=1 G4=1 G5=1 G6=1 SE=1 FE=1 LV=1 SL=1
1R=0
nt Te a
U1,U2=0
m
of P
NmNI=00,01,10,11
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The TEMUX 84 provides two loopback modes for T1/E1 links to aid in network and system diagnostics. The internal T1/E1 line loopback can be initiated at any time via the P interface, but is usually initiated once an inband loopback activate code is detected. The system Diagnostic Digital loopback can be initiated at any
Co
12.13 T1/E1 Framer Loopback Modes
nt e
ar
LB=1
tm
Slip Event 1. This bit is always zero if the ELSTBYP bit of the RX-SBI-ELST Indirect Channel Data register has been set to logic 1. When H-MVIP only mode is set (i.e. SYSOPT=01), the slips are relative to the CMV16MCLK input. Otherwise, the slips are relative to the SREFCLK. Payload Loopback Activated. TEMUX 84 doesn't perform payload loopbacks; therefore, this bit is always encoded as 0. Under Study For Synchronization. Reserved ( Default Value =0)
One second Report Modulo 4 Counter
in
er
In
co
n
Line code violation event 1. This bit is always encoded as 0.
Tu
es
Frame Synchronization Bit Error Event 1 (SE shall=0 )
da
y,
Severely Errored Framing Event 1(FE shall =0)
14
Se
100pt
em
be
r,
20
04
G1=1
CRC ERROR EVENT =1
07
Bit Value
Interpretation
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Table 23
- Performance Report Message Contents
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TTOP
TRAP
co
M13 M 13 VTPP
INSBI (byte) TTM P (bit)
n
Telecom Bus
Line Loopback
Tu
M13 M 13 D3M A
M13 M 13 DS3 TRAN
M13 M13 M13
M13 M13 PISO
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da
LIUs
y,
14
Figure 29
- T1/E1 Line Loopback
Se
T1/E1 Line loopback is initiated by setting the LLOOP bit to a 1 through the TJAT Indirect Channel Data register. When in line loopback mode, the appropriate T1/E1 framer in the TEMUX 84 is configured to internally connect the jitterattenuated clock and data from the RJAT to the transmit clock and data going to the M13 mux and SONET/SDH mapper. The RJAT must not be bypassed except for SONET/SDH byte synchronously mapped tributaries. Conceptually, the data flow through a single T1/E1 framer in this loopback condition is illustrated in Figure 29.
pt
em
be
r,
20
04
07
Ingress H-MVIP T1/E1 ELST84 T1/E1 SIGX84 EXSBI
T1/E1 Line Loopback
:4
H-M VIP
In
T1/E1 JAT84 T1/E1 JAT84
T1/E1 TRAN84 T1/E1 FRMR84
3:
time by the system via the P interface to check the path of system data through the framer.
in
M13 M 13 VTPP
M 13 M13 RTOP/ RTTB
RTDM (bit)
er
Telecom Bus
tm
EXSBI (byte)
T1/E1 ELST84
INSBI Egress H-MVIP
26
LIUs
T1/E1 Diagnostic Digital Loopback When Diagnostic Digital loopback is initiated, by writing a 1 to the DLOOP bit through the RJAT Indirect Channel Data register, the appropriate T1/E1 framer in the TEMUX 84 is configured to internally connect its transmit clock and data to the receive clock and data The data flow through a single T1/E1 framer in this loopback condition is illustrated in Figure 30.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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M13 M 13 D3M D
M13 M 13 DS3 FRMR
M13 M13 M13
ar
M13 M13 SIPO
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
SBI 155
H-M VIP
216
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
M13 M 13 D3M A
M13 M 13 VTPP
TTOP
TRAP
be
TTM P (bit) M13 M 13 VTPP M 13 M13 RTOP/ RTTB RTDM (bit) EXSBI (byte) M13 M 13 DS3 FRMR M13 M13 M13 M13 M13 SIPO
T1/E1 JAT84 T1/E1 JAT84
T1/E1 TRAN84 T1/E1 FRMR84
T1/E1 ELST84 T1/E1 SIGX84
r,
20
Telecom Bus
04
M13 M 13 DS3 TRAN
M13 M13 M13
M13 M13 PISO
07
Ingress H-MVIP EXSBI
:4
INSBI (byte)
LIUs
3:
H-M VIP SBI 155
INSBI Egress H-MVIP
em
Do wn lo
DS3 and E3 Diagnostic Loopback allows the transmitted DS3 or E3 stream to be looped back into the receive DS3 or E3 path, overriding the DS3 or E3 stream received on the RDAT/RPOS and RNEG/RLCV inputs. The RCLK signal is also substituted with the transmit DS3 or E3 clock, TCLK. The configuration of the receive interface determines how the TNEG/TMFP signal is handled during loopback: if the UNI bit in the DS3 FRMR register is set, then the receive interface is configured for RDAT and RLCV, therefore the TNEG/TMFP signal is suppressed during loopback so that transmit MFP indications will not be seen nor accumulated as input LCVs. If the UNI bit is clear, then the interface is configured for bipolar signals RPOS and RNEG, therefore the TNEG is fed directly to the RNEG input. This diagnostic loopback can be used when the TEMUX 84 is configured as a multiplexer or as a framer only. The DS3/E3 loopback mode is shown diagrammatically in Figure 31.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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ed
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Co
nt e
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m
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DS3 and E3 Diagnostic Loopback
tm
The TEMUX 84 provides two E3 and three DS3 M13 multiplexer loopback modes to aid in network and system diagnostics at the DS3 interface. The DS3 loopbacks can be initiated via the P interface whenever the DS3 framer/M13 multiplexer is enabled. The DS3 and E3 Master Data Source register controls the DS3 loopback modes. These loopbacks are also available when the DS3 mux is used with the DS3 mapper via the telecom bus interface.
in
er
In
co
n
Tu
es
12.14 DS3 and E3 Loopback Modes
da
y,
LIUs
14
M13 M 13 D3M D
Se
Telecom Bus
Diagnostic Loopback
pt
T1/E1 ELST84
26
H-M VIP
217
Figure 30
- T1/E1 Diagnostic Digital Loopback
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
RCLK RPOS/ RDAT RNEG / RLCV
Do wn lo
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Co
nt e
DS3 and E3 Line Loopbacks allow the received DS3/E3 streams to be looped back into the transmit DS3/E3 paths, overriding the DS3/E3 streams created internally by the framing unchannelized data or multiplexing of the lower speed tributaries. The transmit signals on TPOS/TDAT and TNEG/TMFP are substituted with the receive signals from RPOS/RDAT and RNEG/RLCV. The TCLK signal is also substituted with the receive DS3/E3 clock, RCLK. While this mode is active, AIS may be substituted for the DS3 payload being transmitted on the TPOS/TDAT and TNEG/TMFP outputs. Note that the transmit interface must be configured to be the same as the DS3/E3 FRMR receive interface for this mode to work properly. The DS3/E3 line loopback mode is shown diagrammatically in Figure 32. There is a second form of line loopback which only loops back the DS3/E3 payload. In this mode the DS3 framing overhead is regenerated for the received DS3/E3 stream and then retransmitted. Line loopback is selected with the LLOOP bit in the DS3 and E3 Master Data Source register and payload loopback is selected by the PLOOP bit in the same register.
nt Te a
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In
co
n
Tu
es
DS3 and E3 Line Loopback
da
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TNEG/ TMFP
14
TCLK TPOS/ TDAT
DS3/E3 TRAN
Se
pt
UNI
em
be
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20
04
DS3/E3 FRMR
07
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Figure 31
- DS3/E3 Diagnostic Loopback Diagram
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
RCLK RPOS/ RDAT RNEG / RLCV
TCLK TPOS/ TDAT TNEG/ TMFP
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tm
Figure 33
RCLK RPOS/ RDAT RNEG/ RLCV
- DS2 Loopback Diagram
F MX12 #7 F R MX12 #6 RM FR MX12 #5 M R F MR MX12 #4 RR F M MX12 #3 RR F M MX12 #2 RR F MX12 #1 RM MR R
nt Te a
m
DS3 FRMR MX23
Optional DEMUX AIS Insertion
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
TCLK TPOS/ TDAT TNEG/ TMFP
Co
nt e
DS2 Tributary Loopback path
DS3 TRAN
by
in
er
DS2 Demultiplex Loopbacks allow each of the seven demultiplexed DS2 streams to be looped back into the MX23 and multiplexed up into the transmit DS3 stream. This overrides the tributary DS2 streams coming from the MX12s. The DS2 loopback mode is shown diagrammatically in Figure 33 and is enabled via the MX23 Loopback Activate register.
In
co
n
Tu
es
DS2 Demultiplex Loopback
da
y,
14
DS3/E3 TRAN
Se
pt
em
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20
04
DS3/E3 FRMR
07
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Figure 32
- DS3 and E3 Line Loopback Diagram
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Figure 34
- Telecom Diagnostic Loopback Diagram
er
In
LADATA[7:0] LADP LAPL LAC1J1V1 LAC1
nt Te a
m
of P
ar
LDDATA[7:0] LDDP LDPL LDC1J1
VTPP VT/TU Payload Processor
co
n
The Telecom Bus Diagnostic Loopback allows the transmitted telecom bus stream to be looped back into the receive SONET/SDH receive path, overriding the data stream received on the telecom drop bus inputs. While Telecom diagnostic loopback is active, valid SONET/SDH data continues to be transmitted on the telecom add bus outputs. The entire telecom drop bus is overwritten by the diagnostic loopback even though only one STS-1 SPE, STM-1/VC4 TUG3 or STM-1/VC3 is generated by the egress VTPP onto the telecom add bus. This loopback is only available for VT1.5/VT2/TU11/TU12 mapped tributaries. DS3 mapped tributaries must use the DS3 diagnostic loopback. The telecom bus diagnostic loopback mode is shown diagrammatically in Figure 34.
Tu
es
da
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14
Se
tm
in
ad
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
Telecom Line Loopback The Telecom Bus Line Loopback allows the received telecom drop bus data to be looped back out the telecom add bus after being processed by both the ingress
Co
nt e
pt
em
RTOP Receive Tributary Path O/H
VTPP VT/TU Payload Processor
be
Telecom Diagnostic Loopback
r,
20
The TEMUX 84 provides two loopbacks at the telecom bus interface to aid in network and system diagnostics at the SONET/SDH interface. These loopback modes can be enabled via the microprocessor whenever the SONET/SDH block is enabled as the mapper for the T1/E1 framer slices or as the mapper for the DS3 framer or M13 Multiplexer.
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220
12.15 Telecom Bus Mapper/Demapper Loopback Modes
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PM8316 TEMUX 84
Figure 35
- Telecom Line Loopback Diagram
VTPP VT/TU Payload Processor
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The SBI structure uses a locked SONET/SDH structure fixing the position of the TU-3 relative to the STS-3/STM-1. The SBI is also of fixed frequency and alignment as determined by the reference clock (SREFCLK) and frame indicator signals (SAC1FP and SDC1FP). Frequency deviations are compensated by adjusting the location of the T1/E1/DS3/TVT1.5/TVT2 channels using floating
Co
Multiplexing Structure
nt e
The TEMUX 84 uses the Scaleable Bandwidth Interconnect (SBI) bus as a high density link interconnect with devices processing T1s, E1s, DS3s, E3s, transparent virtual tributaries and arbitrary bandwidth payloads. The SBI bus is a multi-point to multi-point bus capable of interconnecting up to four TEMUX 84 devices in parallel (if connected to a 77.76 MHz bus) with other link layer or tributary processing devices.
nt Te a
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12.16 SBI Bus Data Formats
tm
in
er
In
LADATA[7:0] LADP LAPL LAC1J1V1 LAC1
Tu
es
da
y,
14
Se
LDDATA[7:0] LDDP LDPL LDC1J1
RTOP Receive Tributary Path O/H
VTPP VT/TU Payload Processor
co
n
pt
em
TTOP Transmit Tributary Path O/H
be
r,
20
04
and egress VTPPs. Both VTPP must be setup for the same STS-1 SPE, STM1/VC4 TUG3 or STM-1/VC3 otherwise no loopback data will get through. The ingress data path is not affected by the telecom line loopback. This loopback is only available for VT1.5/VT2/TU11/TU12 mapped tributaries. DS3 mapped tributaries must use the DS3 line loopback. The Telecom bus line loopback mode is shown diagrammatically in Figure 35.
07
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
Co
nt e
nt Te a
m
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tm
in
er
The multiplexed links are separated into three Synchronous Payload Envelopes called SPE1, SPE2 and SPE3. Each envelope carries up to 28 T1s, 21 E1, 28 TVT1.5s, 21 TVT2s, a DS3 or an E3. SPE1 carries the T1s numbered 1,1 through 1,28, E1s numbered 1,1 through 1,21, DS3 number 1,1 or E3 number 1,1. SPE2 carries T1s numbered 2,1 through 2,28, E1s numbered 2,1 through 2,21, DS3 number 2,1 or E3 number 2,1. SPE3 carries T1s numbered 3,1 through 3,28, E1s numbered 3,1 through 3,21, DS3 number 3,1 or E3 number 3,1. TVT1.5s are numbered the same as T1 tributaries and TVT2s are numbered the same as E1 tributaries.
In
co
n
Tu
es
da
y,
14
Table 24 represents a 19.44 Mbit/s signal. The structure is presented on a 77.76 MHz bus by byte interleaving it with three other like structures.
Se
pt
Table 24 shows the bus structure for carrying T1, E1, TVT1.5, TVT2, DS3 and E3 tributaries in a SDH STM-1 like format. Up to 84 T1s, 63 E1s, 84 TVT1.5s, 63 TVT2s, 3 DS3s or 3 E3s are carried within the octets labeled SPE1, SPE2 and SPE3 in columns 16-270. All other octets are unused and are of fixed position. The frame signal (SAC1FP or SDC1FP) occurs during the octet labeled C1 in Row 1 column 7. The Add and Drop buses have independent frame signals to allow for arbitrary alignment of the two buses.
em
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r,
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04
07
tributaries as determined by the V5 indicator and payload signals (SDV5, SAV5, SDPL and SAPL). TVTs also allow for synchronous operation where SONET/SDH tributary pointers are carried within the SBI structure in place of the V5 indicator and payload signals (SDV5, SAV5, SDPL and SAPL).
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PM8316 TEMUX 84
1 Row 1 2
6
7
8
15
16
17
18
19
268 269 270
9
1
2
3
3
- SPE1SPE2SPE3SPE1 5 6 6 6 7
SPE1SPE2SPE3
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* * *
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SPE Column
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Table 25
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Tributary numbering for T1 and E1 uses the SPE number, followed by the Tributary number within that SPE and are numbered sequentially. Table 25 and Table 26 show the T1 and E1 column numbering and relates the tributary number to the SPE column numbers and overall SBI column structure. Numbering for DS3 or E3 follows the same naming convention even though there is only one DS3 or E3 per SPE. TVT1.5s and TVT2s follow the same numbering conventions as T1 and E1 tributaries respectively. SBI columns 16-18 are unused for T1, E1, TVT1.5 and TVT2 tributaries.
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T1#
1,1 2,1 3,1 1,2
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SPE1 Column
7,35,63
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- T1/TVT1.5 Tributary Column Numbering SPE2 Column
7,35,63 7,35,63 8,36,64
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Tributary Numbering
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The TEMUX 84 when enabled for SBI interconnection will add and drop either 28 T1s, 21 E1s, a DS3 or an E3 into each of the three Synchronous Payload Envelopes, SPE1, SPE2 or SPE3. Each SPE is independent of the others. When T1 or E1 tributaries are sourced from the telecom bus via VT1.5, TU11, VT2 or TU12 mappings, the TEMUX 84 also supports a mix of transparent virtual tributaries with T1s and E1s. A restriction to this are that only VT1.5s, TU11s and T1s can be mixed together or VT2s, TU12s and E1s can be mixed together. Another restriction is that the telecom bus and SBI bus must run from the same clock with a fixed framing offset, ie. SREFCLK and LREFCLK are externally connected.
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SPE3 Column
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20
- *** -
-
- *** - SPE1SPE2SPE3SPE1 *** SPE1SPE2SPE3
04
90
- *** - C1 - *** - SPE1SPE2SPE3SPE1 *** SPE1SPE2SPE3
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
07
SBI Column
19,103,187 20,104,188 21,105,189 22,106,190
:4
SBI Column
3:
223
Table 24
- Structure for Carrying Multiplexed Links
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
2,28 3,28
34,62,90 34,62,90
Table 26 E1#
1,1 2,1 3,1 1,2 2,2
***
- E1/TVT2 Tributary Column Numbering SPE1 Column
7,28,49,70 7,28,49,70 8,29,50,71 8,29,50,71 27,48,69,90
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SPE2 Column
SPE3 Column
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7,28,49,70
14
3,21
Tu
2,21
27,48,69,90 27,48,69,90
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1,21
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In Asynchronous modes, timing is communicated across the Scaleable Bandwidth Interconnect by floating data structures within the SBI. Payload indicator signals in the SBI control the position of the floating data structure and therefore the timing. When sources are running faster than the SBI the floating payload structure is advanced by an octet by passing an extra octet in the V3 octet locations (H3 octet for DS3 and E3 mappings). When the source is slower than the SBI the floating payload is retarded by leaving the octet after the V3 or
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In synchronous SBI mode, the T1 DS0s and E1 timeslots are in a fixed format and do not move relative to the SBI structure. The SBI frame pulse, SAC1FP or SDC1FP, in synchronous mode can be enabled to indicate CAS signaling multiframe alignment by pulsing once every 12th 2KHz frame pulse period. SREFCLK sets the ingress rate from the receive elastic store.
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The TEMUX 84 supports both synchronous and asynchronous SBI timing modes. Synchronous modes apply only to T1 and E1 tributaries and are used with ingress elastic stores to rate adapt the receive tributaries to the fixed SBI data rate. Asynchronous modes allow T1, E1, DS3 and transparent tributaries to float within the SBI structure to accommodate differences in timing.
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SBI Timing Master Modes
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07
101,185,269 102,186,270
SBI Column
19,82,145,208 20,83,146,209 21,84,147,210 22,85,148,211 23,86,149,212 79,142,205,268 80,143,206,269 81,144,207,270
:4
1,28
34,62,90
100,184,268
3:
***
26
2,2
8,36,64
23,107,191
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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On the DROP Bus, data received on the FBWDAT[3:1] signals are collected into complete bytes and are presented on SDDATA[7:0] with SDPL asserted high. No flow control is implemented on the DROP bus.
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Data streams of an arbitrary bit rate up to the capacitry of an SPE may be transported across the SPEs to and from the Flexible Bandwidth Ports. When one (or more) of the SBI is programmed to support this, the SAPL and SDPL signals may be asserted and deasserted at arbitrary times to allow precise control of the payload bit rate.
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Arbitrary Bandwidth Support
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On the ADD BUS the TEMUX 84 can be either the timing master or the timing slave. When the TEMUX 84 is the timing slave it receives its transmit timing information from the arrival rate of data across the SBI ADD bus. When the TEMUX 84 is the timing master it signals devices on the SBI ADD bus to speed up or slow down with the justification request signal, SAJUST_REQ. The TEMUX 84 as timing master indicates a speedup request to a Link Layer SBI device by asserting the justification request signal high during the V3 or H3 octet. When this is detected by the Link Layer it will speed up the channel by inserting extra data in the next V3 or H3 octet. The TEMUX 84 indicates a slow down request to the Link Layer by asserting the justification request signal high during the octet after the V3 or H3 octet. When detected by the Link Layer it will retard the channel by leaving the octet following the next V3 or H3 octet unused. Both advance and retard rate adjustments take place in the frame or multi-frame following the justification request.
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On the DROP BUS the TEMUX 84 is timing master as determined by the arrival rate of data over the SBI.
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Transparent VTs can float in the SBI structure in two ways. The first method uses valid V1 and V2 pointers to indicate positive and negative pointer justifications. The second methods uses the SBI signals SDV5, SAV5, SDPL and SAPL to indicate rate adjustments. In the DROP bus, the TEMUX 84 will always provide both valid pointers with valid SDV5 and SDPL signals. On the SBI Add Bus, the TEMUX 84 needs to be configured on a per tributary basis for either transparent VT mode. Transparent VT operation is configured on a per tributary basis via the ETVT and ETVTPTRDIS bits in the TTMP Tributary control registers.
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H3 octet unused. Both these rate adjustments are indicated by the SBI control signals.
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PM8316 TEMUX 84
The TEMUX 84 SBI bus provides a method for carrying link rate information between devices. Two methods are specified, one for T1 and E1 channels and the second for DS3 and E3 channels. For T1 and E1, the link rate information is always generated on the Drop bus and always ignored on the Add bus. For DS3 and E3, only the ClkRate field of the link rate byte is valid on the Drop bus and the use is optional on the Add bus as specified by the CLK_MODE[1:0] bits of the EXSBI Tributary Control Indirect Access Data register. Link rate information is not available for TVTs. These methods use the reference 19.44 MHz SBI clock and the SAC1FP frame synchronization signal to measure channel clock ticks and clock phase for transport across the bus. The T1 and E1 method allows for a count of the number of T1 or E1 rising clock edges between 2 KHz SDC1FP frame pulses. This count is encoded in ClkRate[1:0] to indicate that the nominal number of clocks, one more than nominal or one less than nominal should be generated during the SDC1FP period. This method also counts the number of 19.44 MHz clock rising edges after sampling SDC1FP high to the next rising edge of the T1 or E1 clock, giving the ability to control the phase of the generated clock. The link rate information passed across the SBI bus via the V4 octet and is shown in Table 27. Table 28 shows the encoding of the clock count, ClkRate[1:0], passed in the link rate octet. Note that while the TEMUX 84 generates valid link rate information on the SBI Drop bus, it ignores the V4 byte on the Add bus.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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SBI Link Rate Information
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On the ADD Bus, the EFWBDREQ[3:1] signals request data at a specific rate. The data is read from a shallow FIFO. To keep the FIFO half full, the SAJUST_REQ output is asserted to fetch data across the ADD bus. In turn, the data source responds with data and the SAPL signal asserted an equal or less number of cycles than SAJUST_REQ is asserted. Significant latency is tolerated. Note that the some applications require an exact one-to-one correspondence between SAJUST_REQ and data bytes.
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PM8316 TEMUX 84
SREFCLK T1/E1 CLK
Link Rate Octet T1/E1 Format
Bit #
7 ALM
6
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Clock Count
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***
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***
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Phase
5:4
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3:0 Phase[3:0] ClkRate[1:0] 1024 1025 1023
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The method for transferring DS3 link rate information across the SBI passes the encoded count of DS3 clocks between 2KHz SAC1FP/SDC1FP pulses in the same method used for T1/E1 tributaries, but does not pass any phase information. The other difference from T1/E1 link rate is that ClkRate[1:0] indicates whether the nominal number of clocks are generated or if four fewer or four extra clocks are generated during the SAC1FP/SDC1FP period. The format of the DS3 link rate octet is shown in Table 29. This is passed across the SBI via the Linkrate octet which follows the H3 octet in the column, see Table 35. Table 30 shows the encoding of the clock count, ClkRate[1:0], passed in the link rate octet. N.B. The ClkRate[1:0] information is not valid when the DS3 has been demapped from SONET/SDH by the D3MD function.
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"1x" - Slow
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"01" - Fast
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"00" - Nominal
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ClkRate[1:0]
T1 Clocks / 2KHz 772 771
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Table 28
- SBI T1/E1 Clock Rate Encoding E1 Clocks / 2 KHz
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SDC1FP
***
3:
227
26
Table 27
- SBI T1/E1 Link Rate Information
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PM8316 TEMUX 84
DS3 Format Table 30
ALM
0
ClkRate[1:0]
Unused
- DS3 Clock Rate Encoding DS3 Clocks / 2KHz 22368 22372 22364
ClkRate[1:0] "00" - Nominal "01" - Fast "1x" - Slow SBI Alarms
Table 27 and Table 29 show the alarm indication bit, ALM, as bit 7 of the Link Rate Octet. Devices connecting to the TEMUX 84 which do not support alarm indications must set this bit to 0 on the SBI ADD bus. The presence of an alarm condition is indicated by the ALM bit set high in the Link Rate Octet. For T1 and E1 tributaries, either an out-of-frame condition or Red alarm (persistent out-of-frame) may set the ALM as determined by the IREDEN and IOOFEN per-tributary configuration bits. The absence of an alarm condition is indicated by the ALM bit set low in the Link Rate Octet. In the egress direction the TEMUX 84 can be configured to use the alarm bit to force AIS on a per link basis by the EALMEN or EGRALMEN register bits. For DS3 and E3 Tributaries, the ALM bit reflects the alarm state of the receive tributary if the DS3ALME bit of the DS3/E3 Master Alarm Enable register is set to logic 1. For DS3, the propagated alarms are AIS and idle code with the option of either loss-of-signal and out-of-frame or RED alarm as selected by the REDALME bit of the DS3/E3 Master Alarm Enable register. For E3, the AIS, loss-of-signal and out-of-frame alarms are propagated.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The TEMUX 84 transfers alarm conditions across the SBI for T1, E1 and DS3 tributaries but not valid for transparent VTs.
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Link Rate Octet
Bit #
7
6
5:4
3:0
3:
228
26
Table 29
- DS3 Link Rate Information
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PM8316 TEMUX 84
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COL # 1-18
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Table 31
ROW # 1 2 3 4 5 6 7 8 9
- T1 Framing Format
T1#1,1 19 V1 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22 T1#2,1-3,28 20-102 V1 T1#1,1 103 V5 DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23 T1#2,1-3,28 104-186 T1#1,1 187 PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24 T1#2,1-3,28 188-270 -
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Unused
Unused Unused Unused Unused Unused Unused Unused Unused
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The V1,V2,V3 and V4 octets are fixed to the locations shown. All the other octets, shown shaded for T1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2KHz multi-frame. The position of the floating T1 is identified via the V5 Indicator signals, SDV5 and SAV5, which locate the V5 octet. When the T1 tributary rate is faster than the SBI nominal T1 tributary rate, the T1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the V3 location. When the T1 tributary rate is slower than the nominal SBI tributary rate the T1 tributary is shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the V3 octet and delaying the octet that was originally in that position.
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Table 31 shows the format for mapping 84 T1s within the SPE octets. The DS0s and framing bits within each T1 are easily located within this mapping for channelized T1 applications. It is acceptable for the framing bit to not carry a valid framing bit on the Add Bus since the physical layer device will provide this information. Unframed T1s use the exact same format for mapping 84 T1s into the SBI except that the T1 tributaries need not align with the frame bit and DS0 locations. The V1,V2 and V4 octets are not used to carry T1 data and are either reserved or used for control across the interface. When enabled, the V4 octet is the Link Rate octet of Table 27. It carries alarm and clock phase information across the SBI bus. The V1 and V2 octets are unused and should be ignored by devices listening to the SBI bus. The V5 and R octets do not carry any information and are fixed to a zero value. The V3 octet carries a T1 data octet but only during rate adjustments as indicated by the V5 indicator signals, DV5 and AV5, and payload signals, SDPL and SAPL. The PPSSSSFR octets carry channel associated signaling (CAS) bits and the T1 framing overhead. The DS0 octets are the 24 DS0 channels making up the T1 link.
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229
T1 Tributary Mapping
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PM8316 TEMUX 84
5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
DS0#10 DS0#13 DS0#16 DS0#19 DS0#22 V3 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22 V4 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22
V3 V4 -
DS0#11 DS0#14 DS0#17 DS0#20 DS0#23 R DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23 R DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23
-
DS0#12 DS0#15 DS0#18 DS0#21
07
4
Unused
DS0#7
-
DS0#8
-
DS0#9
04
20
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DS0#24 DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24
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PPSSSSFR
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PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The P1P0S1S2S3S4FR octet carries T1 framing in the F bit and channel associated signaling in the P1P0and S1S2S3S4bits. Channel associated signaling is optional. The R bit is reserved and is set to 0. The P1P0bits are used to indicate the phase of the channel associated signaling and the S1S2S3S4 bits are the channel associated signaling bits for the 24 DS0 channels in the T1. Table 32 shows the channel associated signaling bit mapping and how the phase bits locate the sixteen state CAS mapping for super frame and extended superframe formats. When using four state CAS then the signaling bits are A1-A24, B1-B24, A1-A24, B1-B24 in place of are A1-A24, B1-B24, C1-C24, D1-D24. When using 2 state CAS there are only A1-A24 signaling bits. When the SYNCH_TRIB bit is set for a tributary, the DS0 alignment is precisely as presented in Table 31, and the P1P0 and S1S2S3S4bits in the first row of Table 32 are aligned to the multiframe indicated by the SDC1FP signal, be it an input or output. The F-bit positions in Table 32 have an arbitrary alignment relative to the
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3
Unused
DS0#4
-
DS0#5
-
DS0#6
3:
230
2
Unused
DS0#1
-
DS0#2
-
DS0#3
26
-
1
Unused
V2
V2
R
-
PPSSSSFR
-
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Table 32
S1 A1 A5 A9 A13 A17 A21 B1 B5 B9 B13 B17 B21 C1 C5 C9 C13 C17 C21 D1 D5 D9 D13 D17 D21 S2 A2 A6 A10 A14 A18 A22 B2 B6 B10 B14 B18 B22 C2 C6 C10 C14 C18 C22 D2 D6 D10 D14 D18 D22
- T1 Channel Associated Signaling bits
SF S3 A3 A7 A11 A15 A19 A23 B3 B7 B11 B15 B19 B23 C3 C7 C11 C15 C19 C23 D3 D7 S4 A4 A8 A12 A16 A20 A24 B4 B8 B12 B16 B20 B24 C4 C8 C12 C16 C20 D4 D8 D12 D16 D20 D24 F F1 S1 F2 S2 F3 S3 F4 S4 F5 S5 F6 S6 F1 ESF F M1 C1 M2 F1 M3 C2 M4 F2 M5 C3 F3 M6 P1 P 0 00 00 00 00 00 00 01 01
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M7 C4 M8 F4 M9 C5
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S1 F2 F3
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S2 S3 F4 S4 F5 S5 F6 S6
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M10 F5 M11 C6 M12 F6
D11
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D15
D19 D23
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In synchronous mode the T1 tributary mapping is fixed to that shown in Table 31 and rate justifications are not possible using the V3 octet. The clock rate information within the link rate octet in the V4 location is not used in synchronous mode.
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T1 tributary asynchronous timing is compensated via the V3 octet. T1 tributary link rate adjustments are optionally passed across the SBI via the V4. T1 tributary alarm conditions are optionally passed across the SBI bus via the link rate octet in the V4 location.
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01 01 01 01 10 10 10 10 10 10 11 11 11 11 11 11
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P1P0 bits that will change with each controlled frame slip; that illustrated is only an example. The signaling contained within the robbed bit positions of the DS0s will also have an arbitrary alignment relative to the P1P0 bits.
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PM8316 TEMUX 84
Table 33
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COL # 1-18
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ROW # 1 2 3 4 5 6
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When the SYNCH_TRIB bit is set for a tributary, the timeslot alignment is precisely as presented in Table 33.
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- E1 Framing Format
19 V1 TS#1 TS#5 TS#9 20-81 V1 82 V5 TS#2 TS#6 TS#10 TS#14 TS#18 83-144 145 PP TS#3 TS#7 TS#11 TS#15 TS#19 146-207 208 TS#0 TS#4 TS#8 TS#12 TS#16 TS#20 209-270 -
E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21
Unused Unused Unused Unused Unused Unused
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TS#13 TS#17
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The V1,V2,V3 and V4 octets are fixed to the locations shown. All the other octets, shown shaded for E1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2KHz multi-frame. The position of the floating E1 is identified via the V5 Indicator signals, SDV5 and SAV5, which locate the V5 octet. When the E1 tributary rate is faster than the E1 tributary nominal rate, the E1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the V3 location. When the E1 tributary rate is slower than the nominal rate the E1 tributary is shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the V3 octet and delaying the octet that was originally in that position.
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Table 33 shows the format for mapping 63 E1s within the SPE octets. The timeslots and framing bits within each E1 are easily located within this mapping for channelized E1 applications. It is acceptable for the framing bits to not carry valid framing information on the Add Bus since the physical layer device will provide this information. Unframed E1s use the exact same format for mapping 63 E1s into the SBI except that the E1 tributaries need not align with the timeslot locations associated with channelized E1 applications. The V1,V2 and V4 octets are not used to carry E1 data and are either reserved or used for control information across the interface. When enabled, the V4 octet carries clock phase information across the SBI. The V1 and V2 octets are unused and should be ignored by devices listening to the SBI bus. The V5 and R octets do not carry any information and are fixed to a zero value. The V3 octet carries an E1 data octet but only during rate adjustments as indicated by the V5 indicator signals, SDV5 and SAV5, and payload signals, SDPL and SAPL. The PP octets carry channel associated signaling phase information and E1 multiframe alignment. TS#0 through TS#31 make up the E1 channel.
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232
E1 Tributary Mapping
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PM8316 TEMUX 84
2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
TS#1 TS#5 TS#9 TS#13 TS#17 TS#21 TS#25 TS#29 V3 TS#1 TS#5 TS#9 TS#13 TS#17 TS#21 TS#25 TS#29 V4 TS#1 TS#5 TS#9 TS#13 TS#17 TS#21 TS#25 TS#29
V3 V4 -
TS#2 TS#6 TS#10 TS#14 TS#18 TS#22 TS#26 TS#30 R TS#2 TS#6 TS#10 TS#14 TS#18 TS#22 TS#26 TS#30 R TS#2
-
TS#3 TS#7 TS#11 TS#15 TS#19 TS#23 TS#27 TS#31 PP TS#3 TS#7
-
TS#4 TS#8 TS#12 TS#16 TS#20 TS#24 TS#28 R TS#0 TS#4 TS#8 TS#12 TS#16 TS#20 TS#24 TS#28 R TS#0 TS#4 TS#8 TS#12 TS#16 TS#20 TS#24 TS#28 R
20
r,
be
em
pt
Se
14
da
TS#15 TS#19 TS#23 TS#27 TS#31 PP TS#3 TS#7 TS#11 TS#15 TS#19 TS#23 TS#27 TS#31
y,
TS#11
es
Tu
n
co
In
er
TS#6
in
TS#10 TS#14 TS#18 TS#22 TS#26 TS#30
tm
ar
of P
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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ed
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When using channel associated signaling (CAS) TS#16 carries the ABCD signaling bits and the timeslots 17 through 31 are renumbered 16 through 30. The PP octet is 0h for all frames except for the frame which carries the CAS for timeslots 15/30 at which time the PP octet is C0h. The first octet of the CAS multi-frame, RRRRRRRR, is reserved and should be ignored by the receiver when CAS signaling is enabled. Table 34 shows the format of timeslot 16 when carrying channel associated signaling.
Co
nt e
nt Te a
m
04
07
-
1
Unused
V2
V2
R
-
PP
-
TS#0
-
:4
9
Unused
TS#29
-
TS#30
-
TS#31
-
R
-
3:
233
8
Unused
TS#25
-
TS#26
-
TS#27
-
TS#28
-
26
7
Unused
TS#21
-
TS#22
-
TS#23
-
TS#24
-
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ABCD1 ABCD2 ABCD3 ABCD4 ABCD5 ABCD6 ABCD7 ABCD8 ABCD9 ABCD10 ABCD11 ABCD12 ABCD13 ABCD14 ABCD15
ABCD16 ABCD17 ABCD18 ABCD19 ABCD20 ABCD21 ABCD22 ABCD23 ABCD24 ABCD25 ABCD26 ABCD27 ABCD28 ABCD29 ABCD30
00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0
DS3 Tributary Mapping Table 35 shows a DS3 tributary mapped within the first synchronous payload envelope SPE1. The V5 indicator pulse identifies the V5 octet. The DS3 framing format does not follow an 8KHz frame period so the floating DS3 multi-frame located by the V5 indicator, shown in heavy border grey region in Table 35, will jump around relative to the H1 frame on every pass. In fact the V5 indicator will often be asserted twice per H1 frame, as is shown by the second V5 octet in Table 35. The V5 indicator and payload signals indicate negative and positive rate adjustments which are carried out by either putting a data byte in the H3 octet or leaving empty the octet after the H3 octet.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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ed
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Co
nt e
nt Te a
m
of P
ar
In synchronous mode the E1 tributary mapping is fixed to that shown in Table 33 and rate justifications are not possible using the V3 octet. The clock rate information within the link rate octet in the V4 location is not used in synchronous mode.
tm
in
er
In
E1 tributary asynchronous timing is compensated via the V3 octet. E1 tributary link rate adjustments are optionally passed across the SBI via the V4 octet. E1 tributary alarm conditions are optionally passed across the SBI bus via the link rate octet in the V4 location.
co
n
Tu
es
da
y,
14
Se
pt
em
be
r,
20
04
07
:4
RRRR
RRRR
00
3:
234
TS#16[0:3]
TS#16[4:7]
PP
26
Table 34
- E1 Channel Associated Signaling bits
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ROW 1 2 3 4 5 6 7 8 9
1,4,7,10 Unused Unused Unused Unused Unused Unused Unused Unused
13 H1 H2 H3 Unused Unused Unused Unused Unused
16 V5 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3
*** DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3
184 DS3 DS3 DS3 DS3 DS3 DS3 DS3 V5 DS3
*** DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3
268 DS3 DS3 DS3
em
pt
Se
Table 36
Octet # Data
- DS3 Block Format
m
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1
of P
Because the DS3 tributary rate is less than the rate of the grey region, padding octets are interleaved with the DS3 tributary to make up the difference in rate. Interleaved with every DS3 multi-frame are 35 stuff octets, one of which is the V5 octet. These 35 stuff octets are spread evenly across seven DS3 subframes. Each DS3 subframe is eight blocks of 85 bits. The 85 bits making up a DS3 block are padded out to be 11 octets. Table 36 shows the DS3 block 11 octet format where R indicates a stuff bit, F indicates a DS3 framing bit and I indicates DS3 information bits. Table 37 shows the DS3 multi-frame format that is packed into the grey region of Table 35. In this table V5 indicates the V5 octet which is also a stuff octet, R indicates a stuff octet and B indicates the 11 octet DS3 block. Each row in Table 37 is a DS3 multi-frame. The DS3 multi-frame stuffing format is identical for 5 multi-frames and then an extra stuff octet after the V5 octet is added every sixth frame.
ar
tm
2
in
er
In
3
co
n
4
Tu
es
da
5
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14
6
7
be
Unused Linkrate
DS3 DS3 DS3 DS3 DS3 DS3
8
r,
20
04
9 10 11
RRRFIIII
8*I
8*I
8*I
8*I
8*I
8*I
8*I
8*I
07
8*I 8*I
SBI COL#
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
:4
COL #
1
2-56
57
58-84
Col 85
3:
235
SPE
DS3
DS3
DS3
DS3
DS3
26
Table 35
- DS3 Framing Format
AM
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
V5 V5 V5 V5 V5 V5
4*R 4*R 4*R 4*R 4*R 5*R
8*B 8*B 8*B 8*B 8*B 8*B
5*R 5*R 5*R 5*R 5*R 5*R
8*B 8*B 8*B 8*B 8*B 8*B
5*R 5*R 5*R 5*R 5*R 5*R
8*B 8*B 8*B 8*B 8*B 8*B
5*R 5*R 5*R 5*R 5*R 5*R
8*B 8*B 8*B 8*B 8*B 8*B
5*R 5*R 5*R 5*R 5*R 5*R
8*B 8*B 8*B 8*B 8*B 8*B
5*R 5*R 5*R
8*B
3:
26
5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B
Table 37
- DS3 Multi-frame Stuffing Format
20
5*R 5*R 5*R
04
be
r,
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Co
nt e
nt Te a
m
of P
Table 38 shows a E3 tributary mapped within the first synchronous payload envelope SPE1. The V5 indicator pulse identifies the V5 octet. The E3 framing format does not follow an 8KHz frame period so the floating frame located by the V5 indicator and shown in grey in Table 38, will jump around relative to the H1 frame on every pass. In fact the V5 indicator will be asserted two or three times per H1 frame, as is shown by the second and third V5 octet in Table 38. The V5 indicator and payload signals indicate negative and positive rate adjustments which are carried out by either putting a data byte in the H3 octet or leaving empty the octet after the H3 octet.
ar
tm
in
er
In
co
n
Tu
es
E3 Tributary Mapping
da
y,
DS3 asynchronous timing is compensated via the H3 octet. DS3 link rate adjustments are optionally passed across the SBI via the Linkrate octet (N.B. The ClkRate[1:0] information is not valid when the DS3 has been demapped from SONET/SDH by the D3MD function.). DS3 alarm conditions are optionally passed across the SBI bus via the Linkrate octet.
14
Se
pt
em
07
8*B 8*B 8*B 8*B 8*B
:4
AM
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236
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ROW 1 2 3 4 5 6 7 8 9
1,4,7,10 Unused Unused Unused
13 H1 H2 H3
16 V5 E3 E3 E3 E3 E3 E3 E3 E3
*** E3 E3 E3 E3 E3 E3 E3 E3 E3
70 E3 E3 E3 V5 E3 E3 E3 E3 E3
*** E3 E3 E3 E3 E3 E3 E3 E3 E3
130 E3 E3 E3 E3 E3 E3 V5 E3 E3
*** E3 E3 E3 E3 E3 E3 E3 E3 E3
268 E3 E3 E3 E3
Unused Linkrate Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
pt
Se
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
Because the E3 tributary rate is less than the rate of the gray region, padding octets are interleaved with the E3 tributary to make up the difference in rate. Interleaved with every E3 frame is an alternating pattern of 81 and 82 stuff octets, one of which is the V5 octet. These 81 or 82 stuff octets are spread evenly across the E3 frame. Each E3 subframe is 48 octet which is further broken into 4 equal blocks of 12 octets each. Table 39 shows the alternating E3 frame stuffing format that is packed into the gray region of Table 38. Note that there are 6 stuff octets after the V5 octet in one frame and 5 stuff octets after the V5 octet in the next frame. In this table V5 indicates the V5 octet which is also a stuff octet, R indicates a stuff octet, D indicates an E3 data octet, FAS indicates the first byte of the 10 bit E3 Frame Alignment Signal.
ar
tm
in
er
In
co
n
Tu
es
da
When carrying framed E3, only the ITU-T Rec. G.751 format is supported. Unframed E3 is carried clear channel.
y,
14
em
E3 E3 E3 E3 E3
be
r,
20
04
07
SBI COL#
:4
COL #
1
2-18
19
20-38
39
40-84
85
3:
237
SPE
E3
E3
E3
E3
E3
E3
E3
26
Table 38
- E3 Framing Format
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
V5
6*R 5*R 5*R 5*R
FAS
11*D
5*R 5*R 5*R 5*R 5*R 5*R 5*R 5*R
12*D 12*D 12*D 12*D 12*D 12*D 12*D 12*D
5*R 5*R 5*R 5*R 5*R 5*R 5*R 5*R
12*D 12*D 12*D 12*D 12*D 12*D 12*D 12*D
5*R 5*R 5*R 5*R 5*R 5*R 5*R
12*D 12*D 12*D 12*D 12*D
12*D 12*D 12*D FAS 11*D
5*R 5*R 5*R
12*D 12*D 12*D
Se
5*R
Flexible Bandwidth Mapping
Transparent VT1.5/TU11 Mapping VT1.5 and TU11 virtual tributaries, TVT1.5s, are transported across the SBI bus in a similar manner to the T1 tributary mapping. Table 40 shows the transparent structure where "I" is used to indicate information bytes. There are two options when carrying virtual tributaries on the SBI bus, the primary difference being how the floating V5 payload is located. The first option is locked TVT mode which carries the entire VT1.5/TU11 virtual tributary indicated by the shaded region in Table 40. Locked is used to indicate that the location of the V1,V2 pointer is locked. The virtual tributary must have a valid V1,V2 pointer to locate the V5 payload. In this mode the V5 indicator and payload signals, SDV5, SAV5, SDPL and SAPL, may be generated but must be ignored by the receiving device. In locked mode timing is always sourced by the
Do wn lo
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ed
by
Co
nt e
nt Te a
m
of P
When the OPMODE_SPEx[2:0] register bits for an SPE are binary 100, the SBI is configured to transport an arbitrary bandwidth up to the capacity of an SPE. In this mode the SDPL and SAPL signals identify individual valid bytes. For each SPE, every third byte in columns 16 through 270, inclusive, has the potential for presenting data. Be aware that although columns 13 though 15 carry no payload, the byte positions for rows 1 through 4 are driven by the Drop bus with SDPL unconditionally low.
ar
tm
in
er
In
co
n
Tu
es
E3 asynchronous timing is compensated via the H3 octet. E3 link rate adjustments are optionally passed across the SBI via the Linkrate octet. E3 alarm conditions are optionally passed across the SBI bus via the Linkrate octet.
da
y,
14
pt
em
12*D 12*D 12*D
be
V5
5*R
r,
20
04
07
:4
3:
238
Table 39
- E3 Frame Stuffing Format
26
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
V1 I I I I I I I I
V1 V2 V3 -
Tu
ROW #
1-18
19
20-102
es
COL #
VT1.5#1,1
#2,1-3,28
VT1.5#1,1 103 V5 I I I I I I I I I I I I I I I I I I I I I
da
Table 40
- Transparent VT1.5/TU11 Format
#2,1-3,28 104-186 VT1.5#1,1 187 I I I I I I I I I I I I I I I I I I I I I I #2,1-3,28 188-270 -
m
nt Te a
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
of P
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V2 I I I I I I I I V3 I I I
tm
in
er
In
co
n
y,
14
The TEMUX 84 supports both TVT modes simultaneously in the SBI DROP bus and is configurable on a per tributary basis in the SBI ADD bus.
Se
pt
The second option is floating TVT mode which carries the payload comprised of the V5 and I octets within the shaded region of Table 40. In this mode the V1,V2 pointers are still in a fixed location and may be valid but are ignored by the receiving device. The V5 indicator and payload signals, SDV5, SAV5, SDPL and SAPL, must be valid and are used to locate the floating payload. The justification request signal can be used to control the timing on the add bus. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in Table 40.
em
be
r,
20
04
07
transmitting side, therefore justification requests are not used and the SAJUST_REQ signal is ignored. Other than the V1 and V2 octets which must carry valid pointers, all octets can carry data in any format. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in Table 40.
:4
3:
26
AM
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239
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
9 1 2 3 4 5 6 7 8 9
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
I V4 I I I I I I I I
V4 -
I I I I I I I I I I
-
I I I I I I I I I I
07 04
8
Unused
I
-
I
-
I
20
be
r,
em
pt
Se
14
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
The second option is floating TVT mode which carries the payload comprised of the V5 and I octets within the shaded region of Table 41. In this mode the V1,V2 pointers are still in a fixed location and may be valid but are ignored by the receiving device. The V5 indicator and payload signals, SDV5, SAV5, SDPL and SAPL, must be valid and are used to locate the floating payload. The justification
Co
The first option is locked TVT mode which carries the entire VT2/TU12 virtual tributary indicated by the shaded region in Table 41. The term locked is used to indicate that the location of the V1,V2 pointer is locked. The virtual tributary must have a valid V1,V2 pointer to locate the V5 payload. In this mode the V5 indicator and payload signals, SDV5, SAV5, SDPL and SAPL, are optionally generated but must be ignored by the receiving device. In locked mode timing is always sourced by the transmitting side, therefore justification requests are not used and the SAJUST_REQ signal is ignored. Other than the V1 and V2 octets which are carrying valid pointers, all octets can carry data in any format. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in Table 41.
nt e
nt Te a
m
of P
ar
tm
Table 41shows the transparent structure where "I" is used to indicate information bytes. There are two options when carrying virtual tributaries on the SBI bus, the primary difference being how the floating V5 payload is located.
in
er
In
co
VT2 and TU12 virtual tributaries, TVT2s, are transported across the SBI bus in a similar manner to the E1 tributary mapping. The TEMUX 84 supports both TVT modes simultaneously in the SBI Drop bus and is configurable on a per tributary basis on the SBI ADD bus.
n
Tu
es
da
Transparent VT2/TU12 Mapping
y,
:4
7
Unused
I
-
I
-
I
3:
240
6
Unused
I
-
I
-
I
26
-
5
Unused
I
-
I
-
I
-
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
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tm
in
er
In
co
n
Tu
es
da
y,
14
Se
pt
em
be
r,
20
04
07
The TEMUX 84 supports both TVT modes simultaneously in the SBI DROP bus and is configurable on a per tributary basis in the SBI ADD bus.
:4
3:
request signal can be used to control the timing on the add bus. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in Table 41.
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
241
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ROW # 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7
1-18 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
19 V1 I I I I I I I I V2 I I I I I I I I V3 I I I I I I I I
20-81 V1 V2 V3 V4 -
82 V5 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
83-144 -
145 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
146-207 -
208 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
209-270 -
Unused Unused
nt e
Unused Unused Unused Unused Unused Unused Unused Unused
Co
nt Te a
Unused
by
ed
ad
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
m
V4 I I I I I I
of P
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tm
in
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In
co
n
Tu
es
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14
Se
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em
be
r,
20
04
07
:4
3:
242
COL #
E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21
26
Table 41
- Transparent VT2/TU12 Format
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PM8316 TEMUX 84
Table 43 shows the timeslot and CAS bit H-MVIP format when in E1 mode.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
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tm
in
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In
co
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es
da
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14
Se
The H-MVIP data and Channel Associated Signaling interfaces on the TEMUX 84 are able to carry all the DS0s for the T1s or all timeslots for the E1s. The E1s and T1s may be mixed on a per TUG-3/DS3 basis, so each H-MVIP signal will be carrying only E1 or T1 data. When carrying timeslots from E1s the H-MVIP frame is completely filled with 128 timeslots from four E1s but when carrying DS0s from four T1s there are not enough DS0s to completely fill the 128 byte frame. Table 42 shows how the DS0s and CAS bits of four T1s are formatted in the 128 timeslot H-MVIP frame.
pt
em
be
r,
20
04
07
12.17 H-MVIP Data Format
:4
3:
243
9
Unused
I
-
I
-
I
-
I
-
26
8
Unused
I
-
I
-
I
-
I
-
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
12-15 16-19 20-23 24-27 28-31 32-35 * * * 108-111 112-115 116-119 120-123 124-127
3 Undefined 4 5 6 Undefined * * * 21 22 Undefined
3 Undefined 4 5 6
be
3 4 5 6
r,
8-11
2
2
2
20
4-7
1
1
1
04
0-3
F-bit*
F-bit*
F-bit*
07
Timeslot Number
First T1 DS0 Number
Second T1 DS0 Number
Third T1 DS0 Number
Fourth T1 DS0 Number F-bit* 1 2 3 Undefined 4 5 6 Undefined * * * 21 Undefined 22 23 24
Undefined
es
Tu
* * *
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Undefined
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14
Se
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Undefined * * * 21 Undefined 22 23 24
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In
21 22 23 24
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
* For applications where the F-bit value is not overwritten by the transmitter, the least significant bit (latest in time) of this timeslot may be carried transparently. In the ingress direction (i.e. MVID), the F-bit has an additional latency of 125us relative to the DS0 contents (i.e. It is presented at the beginning of the next frame after the one it was received with).
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m
of P
24
ar
23
tm
in
Undefined
em
:4
3:
26
244
Table 42
- Data and CAS T1 H-MVIP Format
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
12-15 16-19 * * * 120-123 124-127
3 4 * * * 30 31
3 4 * * * 30 31
be
3 4 * * *
r,
8-11
2
2
2
20
4-7
1
1
1
04
0-3
0
0
0
07
Timeslot Number
First E1 TS Number
Second E1 TS Number
Third E1 TS Number
Fourth E1 TS Number 0 1 2 3 4 * * * 30 31
da
y,
14
Se
pt
es
Unused
CGA
tm
OOSMF
in
1
2
er
In
co
In the ingress direction, each CAS timeslot is encoded as follows (time increases to the right):
3 OOF
n
Tu
4 A
5 B
em
30 31
6 C
:4
3:
7
26
8 D 6 B C 7 D 8
245
Table 43
- Data and CAS E1 H-MVIP Format
Co
nt e
In the egress direction, each CAS timeslot is encoded as follows (time increases to the right):
1 2 Unused 3 SIGC[1] 4 SIGC[0] A 5
by
ed
Unused
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If the INBANDCTL bit of the TPCC Configuration register is logic 1, the SIGC[1:0] field takes on the same definition as the SIGC[1:0] context bits programmed
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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The OOF bit is high when the framer has lost frame alignment. The OOSMF bit is high when E1 signaling multiframe alignment has been lost. It is also high when T1 frame alignment has been lost. The CGA bit is high if an integrated AIS or RED alarm has been declared.
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0 1 2 3 4 * * * 20 21 22 23 24 25 26 27
1 2 3 4 * * * 5
1
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H-MVIP Timeslot Number
T1 Number (Ch 24)
E1 Number TS 16
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E1 Number TS 15 1 2 3 4 5 * * * 21
14
CCSID[1], CCSED[1]
CCSID[2], CCSED[2]
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Table 44
- CCS and TS0 H-MVIP Format
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In E1 mode, the H-MVIP Common Channel Signaling interface on TEMUX 84 carries timeslot 16 for ISDN signaling, timeslot 15 and timeslot 31 for V5.2 interfaces. In T1 mode, the CCS H-MVIP interface only carries channel 28. E1 and T1 signaling may be mixed on a DS-3/TUG-3 granularity. Table 44 shows the H-MVIP format for carrying common channeling signaling and Time Slot 0 channels. These formats are fixed so when a signaling or V5.2 channel is not in use the H-MVIP timeslot is filled with all ones.
CCSID[3], CCSED[3] E1 Number TS 31 1 2 3 4 5 * * * 21 undefined undefined undefined undefined undefined undefined undefined
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through the TPCC Indirect Channel Data registers. If INBANDCTL is logic 0, the SIGC[1:0] field is unused
26
TS0ID E1 Number TS0 1 2 3 4 5 * * * 21 undefined undefined undefined undefined undefined undefined undefined
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21 22 23 24 25 26 27 28
undefined undefined undefined undefined undefined undefined undefined
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21
undefined undefined undefined undefined undefined undefined undefined
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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246
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
56 57 * * * 75 76 77 78 79 80 81 82 83 84
57 58 * *
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undefined 43 44 * * * 62 63 undefined undefined undefined undefined undefined undefined undefined undefined
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48
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42
42
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30
23
23
23
26
28
29
22
22
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undefined undefined undefined undefined undefined undefined undefined 43 44 * * * 62 63 undefined undefined undefined undefined undefined undefined undefined undefined
undefined undefined undefined undefined undefined undefined undefined 43 44 * * * 62 63 undefined undefined undefined undefined undefined undefined undefined undefined
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76 77 78 79 80 81 82 83 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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22 23 * * * 41 42
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Generating and detecting repetitive patterns
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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When a repetitive pattern (such as 1-in-8) is to be generated or detected, the PS bit must be set to logic 1. The pattern length register must be set to (N-1), where N is the length of the desired repetitive pattern. Several examples of programming for common repetitive sequences are given below in the Common Test Patterns section.
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The pattern generator consists of a 32 bit shift register and a single XOR gate. The XOR gate output is fed into the first stage of the shift register. The XOR gate inputs are determined by values written to the length register (PL[4:0]) and the tap register (PT[4:0], when the PS bit is low). When PS is high, the pattern detector functions as a recirculating shift register, with length determined by PL[4:0].
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Figure 36
- PRGD Pattern Generator
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The pattern generators can be configured to generate pseudo random patterns or repetitive patterns as shown in Figure 36 below:
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This section applies to the PRBS and fixed pattern generators and detectors accessible through the DS3/E3 PRGD Pseudo Random Pattern Generator and Detector Registers (0x0230 - 0x023F, 0x0330 - 0x033F, 0x0430 - 0x043F) and T1/E1 Pattern Generator and Detector Registers (0x0500 - 0x05B7).
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12.18 DS3 and Full Featured T1/E1 Pattern Generation and Detection
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85
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Common Test Patterns
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The PRGD can be configured to monitor the standardized pseudo random and repetitive patterns described in ITU-T Recommendation O.151. The register configurations required to generate these patterns and others are indicated in Table 45 and Table 46 below:
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For pattern detection, the PRGD will determine if a repetitive pattern of the length specified in the pattern length register exists in the input stream. It does so by loading the first N bits from the data stream, and then monitoring to see if the pattern loaded repeats itself error free for the subsequent 48 bit periods. It will repeat this process until it finds a repetitive pattern of length N, at which point it begins counting errors (and possibly re-synchronizing) in the same way as for pseudo-random sequences. Note that the PRGD does NOT look for the pattern loaded into the Pattern Insertion registers, but rather automatically detects any repetitive pattern of the specified length. The precise pattern detected can be determined by initiating a PRGD update, setting PDR[1:0] = 00 in the PRGD Control register, and reading the Pattern Detector registers (which will then contain the 32 bits detected immediately prior to the strobe).
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For pattern generation, the desired pattern must be written into the PRGD Pattern Insertion registers. The repetitive pattern will then be continuously generated. The generated pattern will be inserted in the output data stream, but the phase of the pattern cannot be guaranteed.
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3:
26
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RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
220 -1 (O.153)
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218 -1
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217 -1
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215 -1 (O.151)
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211 -1 (O.152, O.153)
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210 -1
02
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29 -1 (O.153)
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08
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27 -1 (Fractional T1 LB Deactivate)
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FF FF
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27 -1 (Fractional T1 LB Activate)
03
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FF
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27 -1
00
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26 -1
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01
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FF FF FF FF FF FF
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24 -1
00
03
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23 -1
00
02
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FF
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07
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Pattern Type
TR
LR
IR#1
IR#2
IR#3
IR#4
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3:
TINV RINV 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 09 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
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0A 0E 10 11 13 13 14 15 16 18 1B
0D 02 06 02 10 01 00 11 02 02 01
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220 -1 (O.151 QRSS bit=1)
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223 -1 (O.151) 225 -1 228 -1 229 -1
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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FF FF FF FF FF FF FF FF FF FF FF FF FF
26
250
Table 45
- Pseudo Random Pattern Generation (PS bit = 0)
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PM8316 TEMUX 84
Alternating ones/zeros Double alternating ones/zeros 3 in 24 1 in 16 1 in 8 1 in 4 Inband loopback activate Inband loopback deactivate
00 00 00 00 00 00 00 00
01 03 17 0F 07 03 04
FE FC 22
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All zeros
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All ones
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00
FF
FF
FF
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04
Pattern Type
TR
LR
IR#1
IR#2
IR#3
07
IR#4 FF FF FF FF FF FF FF FF FF FF
:4
Table 46
- Repetitive Pattern Generation (PS bit = 1)
3:
TINV 0 0 0 0 0 0 0 0 0 0 RINV 0 0 0 0 0 0 0 0 0 0
251
FF FF 20 FF FF FF
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01 01
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F1 F0 FC
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FF 00 00
FF FF FF FF
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FF FF
02
TR = PRGD Tap Register
IR#1 = PRGD Pattern Insertion #1 Register IR#2 = PRGD Pattern Insertion #2 Register
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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IR#3 = PRGD Pattern Insertion #3 Register IR#4 = PRGD Pattern Insertion #4 Register The TINV bit and the RINV bit are contained in the PRGD Control register
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LR = PRGD Length Register
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The PS bit and the QRSS bit are contained in the PRGD Control register
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Notes for the Pseudo Random and Repetitive Pattern Generation Tables
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231 -1
02
1E
FF
FF
FF
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0
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
0
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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Bypass Register
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Instruction Register and Decode
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Device Identification Register
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TDI
Boundary Scan Register
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Figure 37
- Boundary Scan Architecture
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The TEMUX 84 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below.
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20
04
Mux DFF
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TDO Control Select Tri-state Enable
252
12.19 JTAG Support
TMS
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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TRSTB TCK
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Test Access Port Controller
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26
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PM8316 TEMUX 84
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register placed in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI, and forced onto all digital outputs.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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12.19.1
TAP Controller
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PM8316 TEMUX 84
0 1 Run-Test-Idle Select-DR-Scan 0 1 Capture-DR 0 1
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Test-Logic-Reset
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TRSTB=0
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1 Select-IR-Scan 0 1 Capture-IR 0 Shift-IR 0 1 1 Exit1-IR 0 Pause-IR 0 0 Exit2-DR 1 Update-DR 1 0 1 Exit2-IR 1 Update-IR 1 0 0 0 1 0
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Exit1-DR 0
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Pause-DR 1 0
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Shift-DR 1
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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All transitions dependent on input TMS
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254
Figure 38
- TAP Controller Finite State Machine
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The run test/idle state is used to execute tests.
Capture-DR
The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Capture-IR
ed
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Shift-IR
The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK.
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The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK.
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Update-DR
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Shift-DR
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The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK.
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Run-Test-Idle
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The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
04
07
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26
255
Test-Logic-Reset
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PM8316 TEMUX 84
The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
BYPASS
EXTEST
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
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SAMPLE
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The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
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The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device.
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The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO.
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Boundary Scan Instructions
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20
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26
256
Update-IR
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The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state.
IDCODE
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Figure 39
- Input Observation Cell (IN_CELL)
Scan Chain Out INPUT to internal logic
Input Pad
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G1 G2
SHIFT-DR
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I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
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In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table in the JTAG Test Port section 11.2.
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Boundary Scan Cells
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Scan Chain In
14
The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out of the output, TDO, using the Shift-DR state.
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STCTEST
04
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26
257
IDCODE
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PM8316 TEMUX 84
EXTEST Output or Enable from system logic IDOODE SHIFT-DR
CLOCK-DR Scan Chain In
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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UPDATE-DR
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I.D. code bit
1 1 1 1
2 2 MUX 2 2
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G1 G2
14
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MUX
20
1
04
07
OUTPUT or Enable
G1
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Scan Chain Out
3:
258
26
Figure 40
- Output Cell (OUT_CELL)
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PM8316 TEMUX 84
07 be r, 20 04
MUX C
Scan Chain Out
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In
G1 1
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INPUT to internal logic OUTPUT from internal logic
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OUTPUT ENABLE from internal logic (0 = drive)
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Figure 42
- Layout of Output Enable and Bidirectional Cells
Scan Chain Out
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OUT_CELL
IO_CELL
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12 1 2 MUX 12 12
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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Scan Chain In
:4
INPUT to internal logic OUTPUT to pin
I/O PAD
3:
259
26
Figure 41
- Bidirectional Cell (IO_CELL)
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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This interface enables high-density, byte-serial SBI connectivity of the TEMUX 84 to PMC-Sierra's high-density T1/E1/J1 line interface units: PM4318 OCTLIU and PM4319 OCTLIU-SH. Further, TEMUX 84's system-side SBI bus will still be available to seamlessly connect to the industry's highest-density link-layer devices, offered by PMC-Sierra, Inc. (S/UNI-IMA, FREEDM, AAL1gator, SBS family of devices).
20
04
07
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3:
26
260
12.20 Configuring the Line Side SBI
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PM8316 TEMUX 84
Figure 43
-Pin Connection Diagram for Line Side SBI
19.44MHz
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TEMUX84
LREFCLK LAC1 LAC1J1V1 LADATA[7:0] NC
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LADP LAOE/LATPL LAV5 LAPL LDC1J1V1 LDDATA[7:0] LDDP LDTPL LDV5 L77 NC
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Using the line side SBI mode essentially means that the device is acting as a T1/E1/J1 Framer only. This line side interface will typically be connected to multiple PMC-Sierra's T1/E1/J1 line interface units, PM4318 OCTLIU or PM4319 OCTLIU-SH. The line side SBI bus is based upon the Byte-Synchronous Mapper mode, currrently documented in the TEMUX 84 Register Descriptions (PMC-2000034).
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
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Software
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04
For the TEMUX 84 to use its line side SBI interface to connect with PM4318 OCTLIU or PM4319 OCTLIU-SH, the pin connection diagram shown below in Figure 43 must be used:
REFCLK C1FPOUT AC1FP ADATA[7:0] ADP APL AV5
DC1FP DDATA[7:0] DDP DPL DV5
07
OCTLIU
:4
3:
261
12.20.1
Hardware
26
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PM8316 TEMUX 84
1. Set IVTPPBYP=1 in Register 0x0701
11. Set Bit 7 in Register 0x0040 to 1
1. Set the TRIB_TYP bits to `01'
When enabling the individual tributaries in the Byte Synchronous Demapper:
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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In additional all TU11 bits in the device must be configured correctly. For T1 operation all TU11 bits must be set to 1, for E1 all TU11 bits must be set to 0. The above-listed register accesses will enable connectivity between the TEMUX 84 device and multiple OCTLIU devices over TEMUX 84's line side SBI interface. The next revision of the production-release TEMUX 84 Software Device Driver will include support for line side SBI.
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Set ENBL=1.
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of P
ar
When enabling the individual tributaries in the Byte Synchronous Mapper:
tm
in
12. Set FI_EMPTY_ENBL=1 in Register 0x09EF
er
In
co
10. Set EPTRBYP[3:1]= `111' in Register 0x0704
n
Tu
9. Set OTUG3=1 in Register 0x0703
es
8. Set LATPLSEL=1 in Register 0x704
da
y,
7. Set Reserved bit 7 in Register 0x0700 to '1'
14
6. Set OTUG3=1 in Register 0x0704
Se
pt
5. Set ITUG3=1 in Register 0x0704
em
4. Set LAV1EN=1 in Register 0x0702
be
r,
3. Set LAJ1EN=1 in Register 0x0702
20
2. Set EVTPPBYP=1 in Register 0x0704
04
07
:4
Therefore, one would essentially configure the TEMUX 84 for Byte Synchronous Mapper mode and with the following modifications to software; the ByteSynchronous Mappers will simulate the SBI bus format:
3:
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
262
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
da
y,
14
Se
pt
em
be
r,
20
04
07
:4
3:
263
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Se
RCLK[x] RPOS[x] RNEG[x]
pt
em
Figure 44
- Receive Bipolar DS3 Stream
be
r,
All functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines (i.e. polarity control bits in the TEMUX 84 registers are set to their default states).
y,
14
3 consec 0s
Figure 45
RCLK[x] RDATI[x] RLCV[x]
- Receive Unipolar DS3 Stream
nt Te a
X1 BIT
m
of P
INFO 1
ar
tm
in
The Receive Bipolar DS3 Stream diagram (Figure 44) shows the operation of the TEMUX 84 while processing a B3ZS encoded DS3 stream on inputs RPOS and RNEG. It is assumed that the first bipolar violation (on RNEG) illustrated corresponds to a valid B3ZS signature. A line code violation is declared upon detection of three consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid B3ZS signature.
er
INFO 84
In
co
n
Tu
es
da
X2 BIT
INFO 84
C BIT
INFO 1
20
INFO 2
04
LCV
07
INFO 3 INFO 4 INFO 5 OR P OR M BIT OR F BIT LCV INDICATION
13.1 DS3 Line Side Interface Timing
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
The Receive Unipolar DS3 Stream diagram (Figure 45) shows the complete DS3 receive signal on the RDAT input. Line code violation indications, detected by an upstream B3ZS decoder, are indicated on input RLCV. RLCV is sampled each bit period. The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV.
by
Co
nt e
:4
3:
264
13
FUNCTIONAL TIMING
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0
0
0
RDATI[x] RLCV[x]
FA1 1
FA1 2
tm
in
INFO X INFO X+1
er
RCLK[x]
In
co
Figure 47
- Receive Unipolar E3 Stream
n
Tu
The Receive Bipolar E3 Stream diagram (Figure 46) shows the operation of the TEMUX 84 while processing an HDB3-encoded E3 stream on inputs RPOS[x] and RNEG[x]. It is assumed that the first bipolar violation (on RNEG[x]) illustrated corresponds to a valid HDB3 signature. A line code violation is declared upon detection of four consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid HDB3 signature.
ar
es
da
INFO N INFO N+1 INFO N+2 INFO N+3 INFO N+4 INFO N+5 INFO N+6 LCV INDICATION
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
The Receive Unipolar E3 Stream diagram (Figure 47) shows the unipolar E3 receive signal on the RDATI[x] input. Line code violation indications, detected by an upstream HDB3 decoder, are indicated on input RLCV. RLCV is sampled each bit period. The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV.
nt e
nt Te a
m
of P
y,
14
Se
pt
RNEG[x]
V
em
LCV
4 consec 0s
be
RPOS[x]
B
0
r,
0
20
RCLK[x]
04
V
07
X
0
0
V
:4
HDB3 Signature Pattern
3:
265
26
Figure 46
- Receive Bipolar E3 Stream
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TPOS[x] TNEG[x]
1 1 0 0 0 1
TDATO[x] TMFP[x]
tm
in
er
TCLK[x]
In
co
TICLK[x]
X1
Nib 1 Bit 4
n
Tu
Figure 49
- Transmit Unipolar DS3 Stream
es
The Transmit Bipolar DS3 Stream diagram illustrates the generation of a bipolar DS3 stream. The B3ZS encoded DS3 stream is present on TPOS and TNEG. These outputs, along with the transmit clock, TCLK, can be directly connected to a DS3 line interface unit. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
da
y,
14
Se
pt
em
Nib 21 Bit 1
X2
Nib 22 Bit 4
be
0
r,
20
04
Nib 1190 Bit 1
TCLK[x]
07
X1 Nib 1 Bit 4
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
The Transmit Unipolar DS3 Stream diagram (Figure 49) illustrates the unipolar DS3 stream generation. The TMFP output marks the M-frame boundary, X1 bit, in the transmit stream. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
nt Te a
m
of P
ar
:4
TICLK[x]
3:
266
26
Figure 48
- Transmit Bipolar DS3 Stream
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TICLK[x]
0
0
The Transmit Bipolar E3 Stream diagram (Figure 50) illustrates the generation of a bipolar E3 stream. The HDB3 encoded E3 stream is present on TPOS and TNEG. These outputs, along with the transmit clock, TCLK, can be directly connected to a E3 line interface unit. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
Figure 51 - Transmit Unipolar E3 Stream
TCLK[x] TDATO[x] TMFP[x]
of P
ar
tm
in
er
TICLK[x]
In
co
n
Tu
INFO X INFO X+1
FA11
FA12
FA13
es
da
INFO X+465
y,
14
Se
TNEG[x]
0
BIP[0]
pt
V
em
TPOS[x]
B
be
0
r,
TCLK[x]
0
BIP[1]
20
BIP[2]
04
V
BIP[3] BIP[4]
07
BIP[5]
X
0
0
V
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
The Transmit Unipolar E3 Stream diagram (Figure 51) illustrates the unipolar E3 stream generation. The TMFP output shown marks the G.832 frame boundary (the first bit of the FA1 frame alignment byte) in the transmit stream. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
Co
nt e
nt Te a
m
:4
HDB3 Signature Pattern
3:
267
26
Figure 50
- Transmit Bipolar E3 Stream
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TICLK[x] TDATI[x] TFPI/TMFPI[x] TFPO/TMFPO[x]
INFO 82
INFO 83
INFO 84
F4
INFO 82
INFO 83
INFO 84
X1
INFO 1
INFO 2
X2
04
07
:4
Figure 52
- Framer Mode DS3 Transmit Input Stream
3:
26
13.2 DS3 and E3 System Side Interface Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
INFO 1
INFO 2
INFO 3
INFO 82
INFO 83
INFO 84
TGAPCLK[x]
es
TDATI[x]
da
y,
14
TICLK[x]
INFO 83
INFO 84
INFO 1
INFO 83
INFO 84
INFO 1
INFO 2
Se
Figure 53
- Framer Mode DS3 Transmit Input Stream With TGAPCLK
pt
INFO 3
em
be
r,
20
INFO 1
INFO 2
INFO 3
INFO 4
INFO 81
INFO 82
INFO 83
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
The Framer Mode DS3 Transmit Input Stream diagram (Figure 52) shows the expected format of the inputs TDAT and TFPI/TMFPI along with TICLK and the output TFPO/TMFPO when the OPMODE_SPEx[2:0] bits are set to "DS3/E3 Framer Only mode" in the SPE Configuration registers. If the TXMFPI bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0, then TFPI is valid, and the TEMUX 84 will expect TFPI to pulse for every DS3 overhead bit with alignment to TDATI. If the TXMFPI register bit is logic 1, then TMFPI is valid, and the TEMUX 84 will expect TMFPI to pulse once every DS3 M-frame with alignment to TDATI. If the TXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0, then TFPO is valid, and the TEMUX 84 will pulse TFPO once every 85 TICLK cycles, providing upstream equipment with a reference DS3 overhead pulse. If the TXMFPO register bit is logic 1, then TMFPO is valid and the TEMUX 84 will pulse TMFPO once every 4760 TICLK cycles, providing upstream equipment with a reference M-frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1, as in Figure 53. TGAPCLK remains high during the overhead bit positions.
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
268
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
RDATO[x] RFPO/RMFPO [x] ROVRHD[x]
INFO 82
INFO 83
INFO 84
F4
INFO 82
INFO 83
INFO 84
X1
INFO 1
INFO 2
X2
07
:4
RSCLK[x]
3:
26
INFO 1 INFO 2 INFO 3 INFO 82 INFO 83 INFO 84
Figure 54
- Framer Mode DS3 Receive Output Stream
Figure 55
RGAPCLK[x] RDATO[x]
- Framer Mode DS3 Receive Output Stream with RGAPCLK
Figure 56
TICLK[x] TDATI[x] TFPI/TMFPI[x]
- Framer Mode G.751 E3 Transmit Input Stream
nt Te a
m
of P
ar
The DS3/E3 Framer Only Mode Receive Output Stream diagram (Figure 54) shows the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD when the OPMODE_SPEx[2:0] bits are set to "DS3/E3 Framer Only mode" in the SPE Configuration registers. Figure 54 shows the data streams when the TEMUX 84 is configured for the DS3 receive format. If the RXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0, RFPO is valid and will pulse high for one RSCLK cycle on first bit of each M-subframe with alignment to the RDATO data stream. If the RXMFPO register bit is a logic 1 (as shown Figure 54), RMFPO is valid and will pulse high on the X1 bit of the RDATO data output stream. ROVRHD will be high for every overhead bit position on the RDATO data stream. Figure 55 shows the output data stream with RGAPCLK in place of RSCLK when the RXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register set to logic 1. RGAPCLK remains high during the overhead bit positions.
tm
in
er
In
co
n
Tu
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
1
es
da
1
y,
1
14
Se
INFO 82
INFO 83
INFO 84
INFO 82
INFO 83
INFO 84
INFO 1
pt
INFO 2
em
be
r,
20
04
AM
Nat
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
INFO 84
INFO 1
INFO 2
INFO 3
INFO 82
INF O 83 INFO 84
1
0
1
0
0
0
0
RA I
bit13
TFPO/TMFPO[x]
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
269
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TGAPCLK[x] TDATI[x]
bit 1530 bit 1531 bit 1532 bit 1533 bit 1534 bit 1535 bit 1536 bit13
04
07
:4
TICLK[x]
3:
bit14
RDATO [x] RFPO /RMFPO [x] ROVRHD[x]
ar
tm
RSCLK[x]
in
er
Figure 58
- Framer Mode G.751 E3 Receive Output Stream
In
co
The Framer Mode G.751 E3 Transmit Input Stream diagrams (Figure 56 and Figure 57) show the expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO (and TGAPCLK) when the TEMUX 84 is configured for the E3 G.751 transmit format. TFPI or TMFPI pulses high for one TICLK cycle and is aligned to the first bit of the frame alignment signal in the G.751 E3 input data stream on TDATI. TFPO or TMFPO will pulse high for one out of every 1536 TICLK cycles, providing upstream equipment with a reference frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1, as in Figure 57. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK.
n
Tu
es
da
y,
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
1
1
14
1
Se
1
pt
0
em
be
1
r,
0
20
0
0
26
Figure 57
- Framer Mode G.751 E3 Transmit Input Stream With TGAPCLK
0
RA I
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Nat
bit13
RGAPCLK[x] RDATO[x]
by
Co
bit 1529
nt e
Figure 59 RGAPCLK
nt Te a
bit 1530 bit 1531
m
- Framer Mode G.751 E3 Receive Output Stream with
bit 1532 bit 1533 bit 1534
of P
bit 1535
bit 1536
bit13
ad Do wn lo
ed
The Framer Mode G.751 E3 Receive Output Stream diagrams (Figure 58 and Figure 59) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
270
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TICLK[x] TDATI[x] TFPI/TMFPI[x] TFPO/TMFPO[x]
FA1 1 FA1 2
y,
14
TGAPCLK[x] TDATI[x]
Do wn lo
The Framer Mode G.832 E3 Transmit Input Stream diagrams (Figure 60 and Figure 61) show the expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO (and TGAPCLK) when the TEMUX 84 is configured for the E3 G.832 transmit format. TFPI or TMFPI pulses high for one TICLK cycle and is aligned to the first bit of the FA1 byte in the G.832 E3 input data stream on TDATI. TFPO or TMFPO will pulse high for one out of every 4296 TICLK cycles, providing upstream equipment with a reference frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1, as in Figure 61. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
Oct 530 1 Oct 530 2 Oct 530 3 Oct 530 4 Oct 530 5 Oct 530 6 Oct 530 7 Oct 530 8
ar
tm
in
TICLK[x]
er
In
Figure 61
- Framer Mode G.832 E3 Transmit Input Stream With TGAPCLK
co
n
Tu
es
da
Oct 530 1 Oct 530 2 Oct 530 3 Oct 530 4 Oct 530 5 Oct 530 6 Oct 530 7 Oct 530 8
FA1 3 FA1 4 FA1 5
Se
Figure 60
- Framer Mode G.832 E3 Transmit Input Stream
pt
em
RGAPCLK), and ROVRHD when the TEMUX 84 is configured for the E3 G.751 receive format. RFPO or RMFPO pulses high for one RSCLK cycle and is aligned to the first bit of the framing alignment signal in the G.751 E3 output data stream on RDATO. ROVRHD will be high for every overhead bit position on the RDATO data stream. If the PYLD&JUST register bit in the E3 FRMR Maintenance Options register is set to logic 0, the Cjk and Pk bits in the RDATO stream will be marked as overhead bits. If the PYLD&JUST register bit is set to logic 1, the Cjk and Pk bits in the RDATO stream will be marked as payload. The RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1. RGAPCLK remains high during the overhead bit positions as shown in Figure 59.
be
FA1 6 FA1 7 FA1 8
r,
20
04
07
:4
3:
26
Oct N 1
AM
Oct N 2
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Oct N 3
Oct N 1
Oct N 2
Oct N 3
271
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
RDATO[x] RFPO/RMFPO[x] ROVRHD[x]
Oct 530 1 Oct 530 2 Oct 530 3 Oct 530 4 Oct 530 5 Oct 530 6 Oct 530 7 Oct 530 8
FA1 1 FA1 2
FA1 3 FA1 4 FA1 5
FA1 6 FA1 7 FA1 8
07
:4
FA2 8
O ct 1 1 Oct 1 2
RSCLK[x]
RGAPCLK[x] RDATO[x]
13.3 Telecom DROP Bus Interface Timing
Do wn lo
Figure 64 shows the function of the various telecom DROP bus signals in AU3 mode when LREFCLK is nominally 19.44 MHz. Data on LDDATA[7:0] is sampled on the rising edge of LREFCLK. The bytes forming the three STS-1 synchronous payload envelopes are identified when the LDPL signal is high. In this diagram, a negative stuff event is shown occurring on STS-1 #2 and a positive stuff event on STS-1 #3. The LDC1J1V1 signal pulses high, while LDPL is set low, to mark the C1 byte of the first STS-1 in every frame of the STS-3 transport envelope. The LDC1J1V1 signal is high when the LDPL signal is high to mark every J1 byte of each of the three STS-1 SPEs. The bytes forming the various tributary synchronous payload envelopes are identified by the LDTPL when set high. The LDV5 signal pulses high to mark the V5 bytes of each tributary. LDTPL and LDV5 are invalid when LDPL is set low. The three STS-1 SPEs can each have
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
The Framer Mode G.832 E3 Receive Output Stream diagrams (Figure 62 and Figure 63) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the TEMUX 84 is configured for the E3 G.832 receive format. RFPO or RMFPO pulses high for one RSCLK cycle and is aligned to the first bit of the FA1 byte in the G.832 E3 output data stream on RDATO. ROVRHD will be high for every overhead bit position on the RDATO data stream. The RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in DS3 and E3 Master Unchannelized Interface Options register is set to logic 1. RGAPCLK remains high during the overhead bit positions as shown in Figure 63.
tm
in
er
In
co
n
Tu
es
da
y,
Oct 530 1 Oct 530 2 Oct 530 3 Oct 530 4 Oct 530 5 Oct 530 6 Oct 530 7
Oct 530 8
14
Se
pt
Figure 63 RGAPCLK
em
- Framer Mode G.832 E3 Receive Output Stream with
be
r,
20
04
3:
Oct 1 1 Oct 1 2
26
272
Figure 62
- Framer Mode G.832 E3 Receive Output Stream
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LREFCLK LDC1J1 **** LDPL LDV5 LDTPL LDDATA[7:0]
INVALID
Se
pt
em
be
r,
INVALID
20
04
X
Figure 64 VCs
- 19.44 MHz Telecom DROP Bus Timing - STS-1 SPEs / AU3
07
:4
different alignments to the STS-3 transport envelope and the alignment is changing for two of the STS-1 SPEs (STS-1 #2 and #3) due to the pointer justification events shown.
3:
X
26
co
n
STS-1 #1 SPE J1 byte Last H4 byte in tributary multiframe
es
A1 A1 A1 A2 A2 A2 C1 C1 C1 J1 C2 H4 Vx
da
y,
INVALID
14
INVALID
H1 H1 H1 H2 H2 H2 H3 H4 H3 G1
AM
X X
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
V5
Negative stuff for STS-1 #2 SPE which happens to carry a non-final H4 byte Positive stuff for STS-1 #3 SPE V5 byte as marked by OTV5
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
The LDV5 and LDTPL signals are optional when using the ingress VTPP within the TEMUX 84 which will regenerate the LDV5 and LDTPL signals from LDC1J1V1, LDPL and the pointers within LDDATA[7:0]. In order to bypass the ingress VTPP, the data on the Telecom drop bus must be locked such that all three STS-1 SPEs are aligned to the STS-3 transport envelope with the J1 bytes immediately following the C1 bytes. This is shown in Figure 65.
of P
ar
tm
in
er
In
Any V1 - V4 byte TU#1, STS-1 #1
Tu
273
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LDPL LDV5 LDTPL LDDATA[7:0]
A2 C1 C1 C1 J1 J1 J1 V1 V1 V1 V1 V1 V1 V1
Se
pt
Figure 66 shows the function of the various telecom DROP bus signals in AU4 mode. Data on LDDATA [7:0] is sampled on the rising edge of LREFCLK. The bytes forming the VC4 virtual container are identified by the setting the LDPL signal high. The LDC1J1V1 signal pulses high, while LDPL is set low, to mark the single C1 byte in every frame of the AU4 transport envelope. The LDC1J1V1 signal is set high again with LDPL high to mark the J1 byte of the VC4. The bytes forming the various tributary synchronous payload envelopes are identified by the LDTPL signal being set high. The LDV5 signal pulses high to mark the V5 bytes of each outgoing tributaries.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
V1 byte VT #1, STS-1 #1 V1 byte VT #1, STS-1 #2 V1 byte VT #1, STS-1 #3
es
da
Implicit location of STS-1 SPE J1 bytes
No stuff events possible J2 byte VT #1, STS-1 #1 V5 byte VT #1, STS-1 #2 V1 bytes VT #2
y,
14
H1 H1 H1 H2 H2 H2 H3 H3 H3
em
be
****
r,
20
04
LDC1J1
07
J2 V5
LREFCLK
:4
3:
274
Figure 65 AU3 VCs
26
- 19.44 MHz Telecom DROP Bus Timing - Locked STS-1 SPEs /
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LDC1J1 **** LDPL LDV5 LDT PL LDDATA [7:0]
INVALID
INVALID
National bytes V5 byte TUG3 #1 Z7 byte TUG3 #1
J1 byte VC 4
14
First NPI byte TUG3 #1
Se
pt
A1 A2 A2 A2 C1 X X
V5
Z7
J1
em
be
NP NP NP
r,
20
04
V1 V1 V1
Figure 67 provides one example of the Telecom Drop bus operating at 77.76 MHz. For specifics on differences to 19.44 MHz operation, refer to the "Notes on 77.76 MHz Telecom Bus Operation" sub-subsection.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
The LDV5 and LDTPL signals are optional when using the ingress VTPP within the TEMUX 84 which will regenerate the LDV5 and LDTPL signals from LDC1J1V1, LDPL and the pointers within LDDATA[7:0]. In order to bypass the ingress VTPP, the position of the single J1 byte and the VC4 is implicitly defined by the C1 byte position. In the locked AU4 mode, the VC4 is defined to be aligned to the AU4 transport envelope such that the J1 byte occupies the first available payload byte after the C1 byte, and no pointer justifications are possible.
in
er
In
co
n
Tu
es
da
y,
V1 byte TU #1, TUG2 #1, TUG3 #1
07
:4
LREFCLK
3:
275
26
Figure 66
- 19.44 MHz Telecom DROP Bus Timing - AU4 VC
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LREFCLK LDC1V1J1 LDPL don't care LDV5 don't care LDTPL don't care LDDATA[7:0]
trib data
J1
07
don't care don't care don't care
:4
J1 Configuration: LSTM1=10, TUG3=0
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
The LATPL signal is updated on the rising edge of LREFCLK. It is output during when the TEMUX 84 is outputing valid tributary data onto the ADD bus. It is asserted high for all bytes making up a tributary and is asserted low during overhead bytes.
ed
by
Co
Figure 68 shows the function of the telecom ADD bus signals in AU3 mode when LREFCLK is nominally 19.44 MHz. Data on LADATA[7:0] is updated on the rising edge of LREFCLK. The LAC1 input is sampled on the rising edge of LREFCLK and aligns all devices on the ADD bus by marking the first C1 byte of the first STS-1 in every fourth STS-3 transport envelope. LAC1 pulses every fourth STS-3 to indicate tributary multiframe alignment on the ADD bus. The bytes forming the three STS-1 synchronous payload envelopes are identified when the LAPL signal is high. The LAC1J1V1 signal pulses high, while LAPL is set low, to mark the C1 byte of the first STS-1 in every frame of the STS-3 transport envelope. The LAC1J1V1 signal is high when the LAPL signal is high to mark every J1 byte of each of the three STS-1 SPEs. The LAV5 signal pulses high to mark the V5 bytes of each tributary. LATPL, multiplexed with LAOE shown separately in Figure 68, indicates valid tributary payload when high. During the V3 location LATPL indicates a negative pointer justification when high and during the byte after the V3 location LATPL low indicates a positive pointer justification. The three STS-1 SPEs have an alignment determined by the SONET/SDH Transmit Pointer Configuration registers. A pointer of 522 decimal is illustrated in Figure 68.
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
da
13.4 Telecom ADD Bus Interface Timing
y,
14
Se
pt
don't care
trib data
em
don't care
don't care
don't care
be
r,
don't care
don't care
don't care
20
don't care
don't care
don't care
don't care
04
3:
276
26
Figure 67
- 77.76 MHz Telecom DROP Bus Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LAOE
****
LAV5 LATPL
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
Figure 69 shows the function of the TEMUX 84 telecom ADD bus when operating in AU4 mode when LREFCLK is nominally 19.44 MHz. In AU4 mode, the position of the single J1 byte and the VC4 is implicitly defined by the LAC1 byte position. The VC4 is defined to be aligned to the AU4 transport envelope such that the J1 byte occupies the first available payload byte after the C1 byte. No pointer justification events take place on the ADD bus. LAC1J1V1 pulses high to mark the first C1 byte, the J1 byte and the third byte after J1 of the first tributary in the AU4 stream. LAPL identifies the payload bytes on LADATA[7:0].
m
of P
ar
tm
in
er
In
co
V1 byte VT #1, STS-1 #1 V1 byte VT #1, STS-1 #2 V1 byte VT #1, STS-1 #3
n
Tu
Implicit location of STS-1 SPE J1 bytes
No stuff events possible J2 byte VT #1, STS-1 #1 V5 byte VT #1, STS-1 #2 V1 bytes VT #2
es
da
LADATA[7:0]
A2 C1 C1 C1 J1 J1 J1 V1 V1 V1 V1 V1 V1 V1
y,
14
Se
pt
LAPL
H1 H1 H1 H2 H2 H2 H3 H3 H3
em
LAC1J1V1
be
r,
20
04
LAC1
07
J2 V5
LREFCLK
:4
3:
277
Figure 68 AU3 VCs
26
- 19.44 MHz Telecom ADD Bus Timing - Locked STS-1 SPEs /
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LAC1 **** LAOE LAC1J1V1 LAPL LAV5 LADATA[7:0]
A2 C1 X X J1 R R R R R R V1
Se
pt
em
First R column of TUG3 #1
co
n
V1 byte TU #1, TUG2 #1, TUG3 #1
Tu
es
National bytes Implicit location of VC4 J1 byte
Last H4 byte in tributary multiframe
da
y,
14
H4
be
r,
20
R R R R R R V5
04
07
Z6
Fixed Stuff Columns V5 byte TU #1, TUG2 #1, TUG3 #1 Z6 byte TU #1, TUG2 #1, TUG3 #3
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
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nt e
nt Te a
m
of P
ar
Figure 70 provides one example of the Telecom Add bus operating at 77.76 MHz. For specifics on differences to 19.44 MHz operation, refer to the "Notes on 77.76 MHz Telecom Bus Operation" sub-subsection.
tm
in
er
In
:4
LREFCLK
3:
278
26
Figure 69
- 19.44 MHz Telecom ADD Bus Timing - Locked AU4 VC Case
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
LREFCLK LAC1
LATPL LADATA[7:0] 0x00 0x00
14
0x00
Se
pt
LAV5
em
LAPL
be
r,
LAC1J1V1
20
LAOE
0x00
04
07
0x00
13.4.1 Notes on 77.76 MHz Telecom Bus Operation
Figure 67 and Figure 70 each illustrate one example set of waveforms; they are not intended to imply constraints on what is possible.
Do wn lo
2. The LAC1J1V1 output is only valid if the LSTM[1:0] bits are "00". The C1 indication will identify the first of the twelve C1 bytes. The nature of the J1 and V1 pulses is dependent on the state of the LAJ1EN, LAV1EN and ECONCAT register bits. The J1 will be high during either the first four J1 bytes or all 12 J1 bytes depending on the state of the ECONCAT bit. The same is true of the V1 pulse. If more than one device is driving the bus, all devices must use the same transmit payload pointer.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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by
Co
nt e
1. Regardless of the state of the LSTM[1:0] bits, the LAC1 input pulse always identifies the first of the twelve C1 bytes.
nt Te a
The following is of special note:
m
of P
ar
Telecom bus operation at 77.76MHz is simply a byte interleaved multiplex of a 19.44 MByte/s stream with idle cycles. The STM-1 of interest is identified by the LSTM[1:0] bits of the Master Bus Configuration register. On the Drop bus, the three unused STM-1s are simply ignored, including parity. On the Add bus, the unused STM-1s are high-impedance by default, but the bus may be configured to drive continuously.
tm
in
er
In
co
n
Tu
es
da
Configuration: LSTM1=01, LADDOE=0, LAJ1EN=1, LATOHEN=1, SC1FPEN=0, TUG3=1, TXPTR='d522
y,
:4
3:
279
26
Figure 70
- 77.76 Telecom ADD Bus Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
4. The INCLDC1J1V1 register bit may only be set if the LSTM[1:0] bits are "00". 5. The Telecom bus becomes unconditionally high-impedance upon either a hardware or software reset. All necessary configuration and at least one LAC1 pulse should precede the setting of the LADDOE or LAOE register bits. 6. If the LADDOE register bit is logic 1, the Add bus signals drive continuously. The LADATA[7:0], LAPL, LATPL, LAV5 outputs will be stable during the STM1 specified by the LSTM[1:0] bits, but they may transition at any time during the byte positions of the other three STM1s. The LAOE output may be used to identify the cycles containing valid data.
Do wn lo
Each tributary in the remote serial alarm port is allocated eight timeslots. The first two timeslots, labeled B1 and B2 in Figure 71, reports the two possible BIP-2 errors in the tributary payload frame. An alarm contributing to remote defect indications is reported in the third timeslot and is labeled D in Figure 71. The timeslot labeled F report alarms contributing to remote failure indications. In extended RDI mode, the D and F bits are considered as two bit codepoint and
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
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nt e
The timing relationships of the signals related to the remote serial alarm port are shown in Figure 71. The remote serial alarm port clocks, RADEASTCK and RADWESTCK, are nominally 9.72 MHz clocks but can range from 1.344 MHz to 10 MHz. The remote serial alarm port frame pulses, RADEASTFP and RADWESTFP, mark the first BIP-2 error bit (B1 in Figure 71) of the first tributary (TU #1 of TUG2 #1, TUG3 #1) on RADEAST and RADWEST, respectively. The frame pulses must be set high to mark every first BIP-2 error bit of the first tributary. Tributaries on RADEAST and RADWEST are arranged in the order of transmission of an STM-1 stream as defined in the references. I.e., TU #1 of TUG2 #1 in TUG3 #1, TU#1 of TUG2 #1 in TUG3 #2, TU#1 of TUG2 #1 in TUG3 #3, TU#1 of TUG2 #2 in TUG3 #1, ... TU #1 of TUG2 #7 in TUG3 #3, TU #2 of TUG2 #1 in TUG3 #1, ... TU #2 of TUG2 #7 in TUG3 #3, TU #3 of TUG2 #1 in TUG3 #1, ... TU #4 of TUG2 #7 in TUG3 #3. Timeslot assignment on RADEAST and RADWEST is unrelated to the configuration of the TUG2. Timeslots are always reserved for four tributaries in every TUG2 even if it is configured for tributaries with higher bandwidth than TU11, such as TU12. At timeslots devoted to non-existent tributaries, for example, tributary 4 of a TUG2 configured for TU12, RADEAST and RADWEST will be ignored.
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
da
13.5 SONET/SDH Serial Alarm Port Timing
y,
14
Se
pt
em
be
r,
20
04
07
:4
3. Up to four devices may be directly connected to the same bus. Current consumption is minimized if all devices are the same (ie. all TEMUX 84s). All devices must receive the same LAC1 signal.
3:
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
280
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Figure 71
RADEASTCK/ RADWESTCK
- Remote Serial Alarm Port Timing
X
RADEASTCK/ RADWESTCK
SC1FP SDDATA[7:0] SDPL
of P
ar
SREFCLK
tm
in
Figure 72
- SBI DROP Bus T1/E1 Functional Timing
*** *** *** *** *** ***
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Figure 72 illustrates the operation of the SBI DROP Bus, using a negative justification on the second to last V3 octet as an example. The justification is indicated by asserting SDPL high during the V3 octet. The timing diagram also
Co
nt e
SDV5
SDDP
nt Te a
m
C1
er
In
13.6 SBI DROP Bus Interface Timing
co
n
RADEAST/ RADWEST
X B1 B2 D
F
X
X
X
Tu
TU #1, TUG2 #1, TUG3 #1
es
TU #1, TUG2 #1, TUG3 #2
F X X X
da
RADEASTFP/ RADWESTFP
y,
14
Se
pt
RADEASTFP/ RADWESTFP
em
TUG3 TUG3 TUG3 TUG3 TUG3 TUG3 TUG3 TUG3 #1 #2 #3 #1 #2 #3 #1 #2
r,
TU #1, TUG 2 #1
TU #1 , TUG 2 #2
TUG2 #3
20
04 be
...
TUG2 #6
07
TU #4, TUG 2 #7 X TUG3 TUG3 TUG3 TUG3 TUG3 #2 #3 #1 #2 #3 TU #1, T UG2 #1, TUG3 #3
X B1 B2 D F X X X
:4
will be reported on the RDI and RFI signals. Out of extended RDI mode, the D and F bits are independent. The remaining four timeslots are unused and are ignored.
3:
26
X B1 B2 D
X B1 B2 D
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
TU #1, TUG2 #2, TUG3 #1
F X X X
V3
V3
V3 DS0#4. V5 DS0#9.
281
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
SDV5 SDDP
*** ***
Figure 73 shows three DS-3 tributaries mapped onto the SBI bus. A negative justification is shown for DS-3 #2 during the H3 octet with SDPL asserted high. A positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3 which has SDPL asserted low. E3 is transported by the same mechanism.
13.7 SBI ADD Bus Interface Timing
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
The SBI ADD bus functional timing for the transfer of tributaries whether T1/E1 or DS3 is the same as for the SBI DROP bus. The only difference is that the SBI ADD bus has one additional signal: the SAJUST_REQ output. The SAJUST_REQ signal is used to by the TEMUX 84 in SBI master timing mode to provide transmit timing to SBI link layer devices.
ar
tm
in
er
In
co
n
Tu
es
da
y,
14
Se
pt
SDDATA[7:0 ] SDPL
***
em
C1
***
H3
H3
H3
be
r,
SC1FP
***
DS-3 #1 DS-3 #2 DS-3 #3 DS-3 #1
20
SREFCLK
***
04
07
Figure 73
- SBI DROP Bus DS3/E3 Functional Timing
:4
3:
shows the location of one of the tributaries by asserting SDV5 high during the V5 octet.
26
AM
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282
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
SC1FP SADATA[7:0] SAPL SAV5 SADP SAJUST_REQ C1
*** *** *** *** *** ***
13.7.1 Notes on 77.76 MHz SBI Bus Operation
1. Regardless of the state of the SSTM[1:0] bits, the SAC1FP and SDC1FP pulses always identify the 25th byte of the frame. 2. Up to four devices may be directly connected to the same bus. Current consumption is minimized if all devices are of the same type (ie. all TEMUX 84s). All devices must receive the same SAC1FP and SDC1FP signals. 3. The SBI bus becomes unconditionally high-impedance upon either a hardware or software reset. All necessary configuration and at least one SDC1FP pulse should precede the setting of the GSOE register bit.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
SBI bus operation at 77.76MHz is simply a byte interleaved multiplex of a 19.44 MByte/s stream with idle cycles. The STM-1 of interest is identified by the LSTM[1:0] bits of the Master Bus Configuration register. On the Add bus, the three unused STM-1s are simply ignored, including parity. On the Drop bus, the unused STM-1s are high-impedance. The following is of special note:
of P
ar
tm
in
er
In
Figure 74 illustrates the operation of the SBI ADD Bus, using positive and negative justification requests as an example. (The responses to the justification requests would take effect during the next multi-frame.) The negative justification request occurs on the DS-3#3 tributary when SAJUST_REQ is asserted high during the H3 octet. The positive justification occurs on the DS-3#2 tributary when SAJUST_REQ is asserted high during the first DS-3#2 octet after the H3 octet.
co
n
Tu
es
da
y,
14
Se
pt
em
be
r,
20
H3
H3
H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
04
07
:4
SREFCLK
***
3:
283
26
Figure 74
- SBI ADD Bus Justification Request Functional Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Figure 75
CMV8MCLK (16 MHz) CMVFPC (4 MHz)
- Egress 8.192 Mbit/s H-MVIP Link Timing
TS 127
tm
MVED[x] CASED[x] CCSED
in
B8
B1
er
B2
In
CMVFPB
co
n
B3
Tu
es
da
B4 TS 0
y,
14
Se
The timing relationship of the common H-MVIP clock, CMV8MCLK, frame pulse clock, CMVFPC, data, MVED[x], CASED[x] or CCSED, and frame pulse, CMVFPB, signals of a link configured for 8.192 Mbit/s H-MVIP operation with a type 0 frame pulse is shown in Figure 75. The falling edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbit/s H-MVIP operation. The TEMUX 84 samples CMVFPB low on the falling edge of CMVFPC and references this point as the start of the next frame. The TEMUX 84 samples the data provided on MVED[x], CASED[x] and CCSED at the 3/4 point of the data bit using the rising edge of CMV8MCLK as indicated for bit 1 (B1) of time-slot 1 (TS 1) in Figure 75. B1 is the most significant bit and B8 is the least significant bit of each octet.
B5
pt
em
B6
be
r,
20
B7
04
07
:4
B8
3:
26
B1 TS 1
284
13.8 Egress H-MVIP Link Timing
13.9 Ingress H-MVIP Link Timing
Do wn lo
The timing relationship of the common 8M H-MVIP clock, CMV8MCLK, frame pulse clock, CMVFPC, data, MVID[x], CASID[x] or CCSID, and frame pulse, CMVFPB, signals of a link configured for 8.192 Mbit/s H-MVIP operation with a type 0 frame pulse is shown in Figure 76. The falling edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbit/s H-MVIP operation. The TEMUX 84 samples CMVFPB low on the falling edge of CMVFPC and references this point as the start of the next frame. The TEMUX 84 updates the data provided on MVID[x], CASID[x] and CCSID on every second falling edge of CMV8MCLK as indicated for bit 2 (B2) of time-slot 1 (TS 1) in Figure 76. The first bit of the next frame is updated on MVID[x], CASID[x] and CCSID on the falling CMV8MCLK clock edge for which CMVFPB is also sampled low. B1 is the most significant bit and B8 is the least significant bit of each octet.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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of P
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AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
When the external device connected to the Egress Flexible Bandwidth port sets the data rate, EFBWDREQ[n] input may be modulated to control the rate bits are emitted on EFBWDAT[n]. In this case as illustrated by Figure 78, the device on the SBI Add bus is expected to respect the SAJUST_REQ output. The TEMUX 84 will assert SAJUST_REQ in an attempt to keep the fill level of the SBI Add bus FIFO at 32 or 256 bytes as determined by the FRACT_THR_HIGH register bit. The SAPL signal is expected to be asserted in response to the SAJUST_REQ assertion. Typically, the 128-byte setting is only used if there is a large latency between the assertion of the SAJUST_REQ output and the corresponding response by SAPL. A one-to-one relationship is not mandatory between SAJUST_REQ and SAPL; additional SAJUST_REQ assertions will be made to achieve the desired rate. A byte is read from the SBI Add bus FIFO for every eight EFBWCLK cycles that EFBWDREQ[n] is asserted high. Provided the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
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nt Te a
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of P
When the data rate is determined by the SBI Add bus device, it ignores the SAJUST_REQ output and asserts the SAPL signal whenever it has data to send. In this situation as illustrated by Figure 77, EFBWDREQ[n] is typically tied high to indicate a willingness to accept all data. With each byte received on the SBI bus, a burst of eight cycles will occur with EFBWEN[n] asserted high to indicate the presence of valid data. Because bytes are transmitted as soon as they are received, latency is minimized.
ar
tm
in
er
In
co
The three Egress Flexible Bandwidth ports provide the ability to transport three arbitrary bit rate data streams across the SBI Add bus. Two regimes are most common: the data rate is set by the device connected to the SBI Add bus (Figure 77) or the data rate is set by the external device connected to this port (Figure 78).
n
Tu
es
da
y,
14
13.10 Egress Flexible Bandwidth Timing
Se
TS 127
TS 0
pt
MVID[x] CASID[x] CCSID TS0ID
B8
B1
B2
B3
B4
B5
em
be
B6
r,
CMVFPB
20
04
B7 B8
CMVFPC (4 MHz)
07
B1 TS 1
CMV8MCLK (16 MHz)
:4
3:
285
26
Figure 76
- Ingress 8.192 Mbit/s H-MVIP Link Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
SBI Add bus responds to the SAJUST_REQ appropriately, the TEMUX 84's SBI Add bus FIFO will remain non-empty and a one-to-one relationship between EFBWDREQ[n] and EFBWEN[n] will be maintained. If for any reason the SBI Add bus FIFO becomes empty, the contemporaneous EFBWDREQ[n] assertions will be disregarded. Figure 78 includes this pathelogical case.
Figure 77 Slave
EFBWCLK[n] EFBWDREQ[n] EFBWEN[n] EFBWDAT[n] valid
da
y,
14
Se
pt
em
be
r,
valid
EFBWEN[n]
nt Te a
m
EFBWDREQ[n]
of P
EFBWCLK[n]
ar
tm
in
Figure 78 Master
er
- Egress Flexible Bandwidth Port Functional Timing - SBI
In
co
N.B. The EFBWEN[n] waveform is not typical. Provided EFBWDREQ[n] is held high, EFBWEN[n] will always be high for at least 8 consecutive EFBWCLK[n] periods.
n
Tu
es
20
- Egress Flexible Bandwidth Port Functional Timing - SBI
nt e
EFBWDAT[n]
valid
13.11 Ingress Flexible Bandwidth Timing
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
The three Ingress Flexible Bandwidth ports provide the ability to transport three arbitrary bit rate data streams across the SBI Drop bus. A bit rate of 48.96 Mbit/s is supported for each port provided the constaints given in the Burst Lengths on
Co
04
valid
last bit available
07
:4
3:
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
286
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Ingress Flexible Bandwidth Port section are respected. It is assumed the devices on the SBI Drop bus are capable of accepting all data presented, as no backpressure flow control is provided. The value on IFBWDAT[n] is accepted as valid whenever IFBWEN[n] is coincidentally sampled as a logic high by IFBWCLK[n]. Figure 79 illustrates typical operation.
IFBWCLK[n] IFBWEN[n] IFBWDAT[n]
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
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by
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nt e
nt Te a
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of P
ar
tm
in
er
In
co
n
Tu
es
da
y,
14
valid
Se
pt
em
be
r,
20
Figure 79
- Ingress Flexible Bandwidth Port Functional Timing
04
07
:4
3:
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
287
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Table 47
- Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature Supply Voltage Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Junction Temperature TST VDD1.8 VDD3.3 VIN
-40 to +85
em
be
Parameter
Symbol
Value
r,
20
04
Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions.
Se
-40 to +125
pt
14
-0.3 to + 3.6 -0.3 to + 5.5 -0.3 to 5.5
y,
da
Tu
es
1000 100 20 +225 +150
n
co
IIN TJ
In
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
2. VDD3.3 should not be allowed to drop below the VDD1.8 voltage level except when VDD1.8 is not powered.
m
of P
1. VDD3.3 should power up before VDD1.8.
ar
tm
Notes on Power Supplies:
in
er
07
C C V C C
Units
VDC VDC VDC mA mA
:4
3:
288
14
ABSOLUTE MAXIMUM RATINGS
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TA = -40C to +85C, VDD3.3 = 3.3V 8%, VDD1.8 = 1.8V 8% (Typical Conditions: TA = 25C, VDD3.3 = 3.3V, VDD1.8 = 1.8V) Table 48
Symbol VDD3.3 VDD1.8 VIL VIH VOL
- D.C. Characteristics
Parameter Power Supply Power Supply Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage Min 2.97 1.65 0 2.0 0 0.1 0.4 Typ 3.3 1.8 Max 3.63 1.95 0.8 Units Volts Volts Volts
14
Volts
Se
y,
Volts
da
es
Tu
n
co
In
in
er
tm
ar
of P
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
pt
em
Guaranteed Input LOW Voltage
Guaranteed Input HIGH Voltage VDD = min, IOL = -4mA for D[7:0], RECVCLK1, RECVCLK2, RECVCLK3, MVID[7:0], CASID[7:0], CCSID, TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1], RGAPCLK/RSCLK[3:1], RDATAO[3:1], RFPO/RMFPO[3:1], ROVRHD[3:1], TFPO/TMFPO/TGAPCLK[3:1], SBIACT, IOL = -8mA for SDDATA[7:0], SDDP, SDPL, SDV5, SAJUST_REQ, SDC1FP, LAC1J1V1, LADATA[7:0], LADP, LAPL, LAOE/LATPL IOL = -2mA for others. Note 3
be
Conditions
r,
20
04
07
:4
3:
289
15
D.C. CHARACTERISTICS
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
IOH = 4mA for D[7:0], RECVCLK1, RECVCLK2, RECVCLK3, TCLK, TPOS/TDAT, TNEG/TMFP, RGAPCLK/RSCLK, RDATAO, RFPO/RMFPO, ROVRHD, MVID[21:1], CASID[21:1], CCSID,
Se
14
Voltage VTH Reset Input Hysteresis Voltage IILPU IIHPU IILPD Input Low Current Input High Current +20 -10
n
In
co
TBD
Tu
VT-
Reset Input Low
es
Voltage
0.6
da
VT+
Reset Input High
2.0
y,
Volts
Volts
Volts
+300 +10 +10
A A A
er
for Input A[12]
for Input A[12]
CIN
nt Te a
IIH
Input High Current Input Capacitance
m
IIL
Input Low Current
of P
IIHPD
Input High Current
ar
tm
Input Low Current
in
-10
+20
+350
A
-10 -10 5
+10 +10
A A pF
COUT
nt e
Output Capacitance Bidirectional Capacitance Operating Current IDD1.8 IDD3.3
5
pF
CIO
Co
5
pF
by
ed
IDDOP1
ad
340 5
500
mA
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
pt
em
IOH = 8mA for SDDATA[7:0], SDDP, SDPL, SDV5, SAJUST_REQ, SDC1FP, LAC1J1V1, LADATA[7:0], LADP, LAPL, LAOE/LATPL IOH = 2mA for others. Note 3
TTL Schmidt
VIL = GND. Notes 1, 3 VIH = VDD. Notes 1, 3 VIL = GND. Notes 3, 4
VIH = VDD. Notes 3, 4
VIL = GND. Notes 2, 3 VIH = VDD. Notes 2, 3 Excluding Package, Package Typically 2 pF Excluding Package, Package Typically 2 pF Excluding Package, Package Typically 2 pF VDD1.8 = 1.94 V VDD3.3 = 3.56 V Outputs Unloaded, Telecom to SBI mode
be
TFPO/TMFPO/TGAPCLK, SBIACT,
r,
20
04
07
Voltage
:4
Bidirectional High
3
3:
290
VOH
Output or
2.4
VDD3.
Volts
VDD = min,
26
Symbol
Parameter
Min
Typ
Max
Units
Conditions
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
DS3 to MVIP mode
2. Input pin or bi-directional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
da
y,
4. Input pin or bi-directional pin with internal pull-down resistor.
14
Se
pt
em
be
1. Input pin or bi-directional pin with internal pull-up resistor.
r,
20
Notes on D.C. Characteristics:
04
07
IDD3.3
5
Outputs Unloaded,
:4
IDD1.8
340
500
mA
VDD3.3 = 3.56 V
3:
291
IDDOP2
Operating Current
VDD1.8 = 1.94 V
26
Symbol
Parameter
Min
Typ
Max
Units
Conditions
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Table 49 Symbol
- Microprocessor Interface Read Access
tSLR tHLR tPRD tZRD tZINTH
Latch to Read Set-up
da
y,
tVL
Valid Latch Pulse Width Latch to Read Hold
14
tHALR
Address to Latch Hold Time
Se
tSALR
Address to Latch Set-up Time
pt
tHAR
Address to Valid Read Hold Time
em
tSAR
Address to Valid Read Set-up Time
be
r,
Parameter
Min
20
04
Max Units
10 5
07
ns ns ns ns ns ns ns 30 20 50 ns ns ns
(TA = -40C to +85C, VDD3.3 = 3.3V 8%, VDD1.8 = 1.8V 8%)
10 10 20 0 5
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
Valid Read Negated to Output Tri-state
In
Valid Read Negated to Output Tri-state
co
Valid Read to Valid Data Propagation Delay
n
Tu
es
:4
3:
292
16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Valid
tS ALR tVL
Address
Se
ALE tSLR
pt
em
tHALR
be
r,
20
es
(CSB+RDB)
da
y,
14
INTB
in
er
In
co
n
Tu
ad
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, and tSLR are not applicable.
Co
nt e
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
nt Te a
Notes on Microprocessor Interface Read Timing:
m
of P
ar
D[7:0]
tm
tPRD
tZ RD
Valid Data
04
tH AR tHLR tZ INTH
A[12:0]
07
tSAR
:4
3:
293
26
Figure 80
- Microprocessor Interface Read Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR
Data to Valid Write Set-up Time Address to Latch Hold Time
da
y,
tSAW
Address to Valid Write Set-up Time Address to Latch Set-up Time
14
Symbol
Parameter
Se
pt
Table 50
- Microprocessor Interface Write Access Min Max Units
em
be
r,
7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
20
04
10 20 10 10 20 0 5 5 5 40
07
6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
:4
3:
26
ns ns ns ns ns ns ns ns ns ns
294
5. Parameter tHAR is not applicable if address latching is used.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
Valid Write Pulse Width
ar
Address to Valid Write Hold Time
tm
Data to Valid Write Hold Time
in
Latch to Write Hold
er
In
Latch to Write Set-up
co
Valid Latch Pulse Width
n
Tu
es
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
A[12:0] tS ALW tV L ALE tSAW (CSB+WRB)
Valid Address
tVWR
Se
pt
em
be
tS LW
da
y,
14
3. Parameter tHAW is not applicable if address latching is used. 4. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable.
of P
ar
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
tm
in
er
Notes on Microprocessor Interface Write Timing:
In
co
n
D[7:0]
Tu
tS DW
es
Valid Data
r,
tHLW
tH DW
20
tH ALW
tH AW
04
07
:4
3:
295
26
Figure 81
- Microprocessor Interface Write Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Table 51 Symbol
- RSTB Timing
Table 52 Symbol
- DS3/E3 Transmit Interface Timing
nt Te a
TTICLK t0TICLK t1TICLK
Instantaneous minimum TICLK[3:1] period
m
fTICLK
E3 TICLK[3:1] average frequency
of P
fTICLK
DS3 TICLK[3:1] average frequency
ar
tm
Description
in
er
In
co
n
Tu
es
da
y,
14
Se
pt
Figure 82
- RSTB Timing
em
tVRSTB
RSTB Pulse Width
100
be
r,
Description
Min
20
04
Max
07
Units
(TA = -40C to +85C VDD3.3 = 3.3V 8%, VDD1.8 = 1.8V 8%)
:4
ns
Max Units
Min
44.736 -50 ppm 34.368 -50 ppm 19.2 7.7 7.7 5
44.736 +50 ppm 34.368 +50 ppm
3:
MHz MHz ns ns ns ns 5
296
17
TEMUX 84 TIMING CHARACTERISTICS
Co
by
tSTFPI
ad
ed
nt e
TICLK[3:1] minimum pulse width low TICLK[3:1] minimum pulse width high
TFPI/TMFPI[x] to TICLK[x] Set-up Time (LOOPT=0, active TICLK edge set by TDATIFALL bit) TFPI/TMFPI[x] to RCLK[x] Set-up Time (LOOPT=1)
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
04
TFPI/TMFPI[x] to RCLK[x] Hold Time (LOOPT=1) tSTDATI TDATI[x] to TICLK[x] Set-up Time (LOOPT = 0, active TICLK edge set by TDATIFALL bit) TDATI[x] to RCLK[x] Set-up Time (LOOPT = 1) tHTDATI
1
07
:4 pt em be r,
5 1 ns 1 2 2 10 10 ns
3: 20
5 ns 2 12 ns 2 2 2 2 -1 -1 2 2 13 4 4 13 13 12 ns ns ns ns ns ns ns
297
tPTFPO
tSTGAP tHTGAP tPTCLK tPTPOS
TDATI[x] to TGAPCLK[x] Set-up Time
Co
tPTNEG
by
ad
ed
tPTPOS2 tPTNEG2
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
nt e
nt Te a
TICLK[x] Edge to TCLK[x] Edge Prop Delay TCLK[x] Edge to TPOS/TDAT[x] Prop Delay
TCLK[x] Edge to TNEG/TMFP[x] Prop Delay TICLK[x] High to TPOS/TDAT[x] Prop Delay (Note 5) TICLK[x] High to TNEG/TMFP[x] Prop D l (N t 5)
m
TDATI[x] to TGAPCLK[x] Hold Time
of P
ar
RCLK[x] to TFPO/TMFPO[x] Prop Delay (LOOPT = 1)
tm
in
TICLK[x] to TFPO/TMFPO[x] Prop Delay (LOOPT = 0, active TICLK edge set by TDATIFALL bit)
er
In
co
n
Tu
tPTGAP
TICLK[x] to TGAPCLK[x] Prop Delay (LOOPT = 0) RCLK[x] to TGAPCLK[x] Prop Delay (LOOPT = 1)
es
da
TDATI[x] to RCLK[x] Hold Time (LOOPT = 1)
y,
14
TDATI[x] to TICLK[x] Hold Time (LOOPT = 0, active TICLK edge set by TDATIFALL bit)
Se
26
tHTFPI
TFPI/TMFPI[x] to TICLK[x] Hold Time (LOOPT=0, active TICLK edge set by TDATIFALL bit)
1
ns
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TFPI/TMFPI
m
of P
TICLK/RCLK
ar
tm
in
er
In
TDATI
co
n
tS TDATI
Tu
es
TICLK/RCLK
da
y,
TFPO/TMFPO
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
tPTFPO
14
Se
tH TDATI
pt
tS TFPI
em
tH TFPI
be
TICLK/RCLK
r,
20
04
Figure 83
- DS3/E3 Transmit Interface Timing
07
Note: The "[x]" implies the parameters for a data signal are only in relation to the associated clock.
:4
3:
26
298
Delay (Note 5)
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TGAPCLK
TGAPCLK tS TGAP
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
da
y,
TDATI
14
Se
tH TGAP
pt
em
be
r,
20
04
tPTGAP
tPTGAP
07
:4
3:
299
TICLK/RCLK
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TCLK
TCLK
TPOS/TDAT
TPOS/TDAT
TNEG/TMFP
TNEG/TMFP
co
TICLK
in
er
tm
In
TCLK
of P
ar
TPOS/TDAT
m
nt Te a
TNEG/TMFP
by
Table 53
Co
nt e
- DS3/E3 Receive Interface Timing Description Min Max Units
ad
ed
Symbol
Do wn lo
fRICLK
DS3 RCLK[3:1] average frequency
n
Tu
TICLK=1, TRISE=X
t TCLK tTCLK P P
t TPOS2 P
t TNEG2 P
es
da
y,
14
t TNEG P
Se
pt
em
t TNEG P
be
t TPOS P
t TPOS P
44.736 -50 ppm
r,
20
04
44.736 +50 ppm
07
:4
MHz
TICLK
TICLK
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
3:
300
26
TICLK=0, TRISE=0
TICLK=0, TRISE=1
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
26
-50 ppm fRICLK TRCLK t0RCLK t1RCLK tSRPOS tHRPOS tSRNEG tHRNEG tPRDATO tPRFPO tPROVRHD tPRGAP E3 RCLK[3:1] average frequency Instantaneous minimum RCLK[3:1] period RCLK[3:1] minimum pulse width low RCLK[3:1] minimum pulse width high RPOS/RDAT[x] Set-up Time RPOS/RDAT[x] Hold Time RNEG/RLCV[x] Set-Up Time RNEG/RLCV[x] Hold Time 34.368 -50 ppm 19.2
+50 ppm
07
:4
34.368+ 50 ppm
3:
2 2 2 2
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
MHz ns ns ns ns ns ns ns ns ns ns ns
em Se pt 14 y, da
RSCLK[x] Edge to RFPO/RMFPO[x] Prop Delay
es
RSCLK[x] Edge to RDATO[x] Prop Delay
nt Te a
m
RCLK
of P
Figure 84
- DS3/E3 Receive Interface Timing
ar
tm
in
RGAPCLK[x] Edge to RDATO[x] Prop Delay
In
RSCLK[x] Edge to ROVRHD[x] Prop Delay
n
Tu
co
er
tS RPOS
tH RPOS
Co
RPOS/RDAT tS RNEG tH RNEG
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
RNEG/RLCV
nt e
be
7.7 4 1 4 1 -2 -2 -2 -2
r,
20
7.7
04
301
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
RDATO
ar
tm
in
RGAPCLK
er
In
co
Dashed line RSCLK represents behaviour when RSCLKR register bit = 1.
nt Te a
m
RDATO
of P
ed
by
Notes on DS3/E3 Interface Timing:
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
1.
Co
When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
nt e
Dashed line RSCLK represents behaviour when RSCLKR register bit = 1.
n
Tu
tP RGAP
es
ROVRHD
da
y,
tPROVRHD
14
Se
RFPO/RMFPO
pt
em
tP RFPO
be
r,
20
04
tP RDATO
07
:4
RSCLK
3:
302
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
3. 4.
LREFCLK Frequency
Tu
es
Symbol
Description
da
y,
Table 54 - Line Side Telecom Bus and Line Side SBI Input Timing - 19.44 MHz (Figure 88) Min Max Units
14
Se
pt
5.
The tPTPOS2 and tPTNEG2 parameters are only applicable when the TICLK bit of the DS3/E3 Master Transmit Line Options register is logic 1.
em
be
Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs except the TCLK[3:1], TPOS/TDAT[3:1] and TNEG/TMFP[3:1] outputs, which have a load of 20pf.
LREFCLK Duty Cycle LREFCLK skew relative to SREFCLK
co
n
19.44 -20 ppm 40 -5 51.84 -50 ppm 44.928 -50 ppm 40
r,
20
04
Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
07
:4
19.44 +20 ppm 60 5 51.84 +50 ppm 44.928 +50 ppm 60
3:
26
2.
When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
MHz % ns MHz MHz % ns ns
nt Te a
tSTEL tHTEL
m
of P
CLK52M Frequency (44.928 MHz) CLK52M Duty Cycle
All Telecom BUS Inputs Set-Up Time 5 to LREFCLK All Telecom BUS Inputs Hold Time to LREFCLK 1
ed
by
Line Side Telecom Bus Input Timing - 77.76 MHz (Figure 88) Symbol Description Min Max Units
ad
Co
nt e
Do wn lo
LREFCLK Frequency
ar
tm
CLK52M Frequency (51.84 MHz)
in
er
In
77.76 -20 ppm
77.76 +20 ppm
MHz
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
303
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tSTEL tHTEL
Figure 85
- Line Side Telecom BUS and Line Side SBI Input Timing
LREFCLK
nt e
nt Te a
m
of P
ar
2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
tm
in
er
In
1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
LAC1, LDDATA[7:0] LDDP,LDPL LDV5,LDC1J1, LDTPL, LDAIS
tS TEL
co
n
Tu
Notes on Telecom and Line Side SBI Input Timing:
es
da
All Telecom BUS Inputs Hold Time to LREFCLK
14
All Telecom BUS Inputs Set-Up Time 3 to LREFCLK
Se
pt
CLK52M Duty Cycle
em
be
CLK52M Frequency (44.928 MHz)
44.928 -50 ppm 40
r,
20
CLK52M Frequency (51.84 MHz)
51.84 -50 ppm
04
LREFCLK skew relative to SREFCLK
07
-4
:4
LREFCLK Duty Cycle
40
60
3:
26
Symbol
Description
Min
Max
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Units
% ns MHz MHz % ns ns
4
51.84 +50 ppm 44.928 +50 ppm 60
y,
0
tH TEL
by
Co
304
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Symbol
Description
da
y,
Table 56 Figure 87)
14
- Telecom Bus Output Timing - 77.76 MHz (Figure 86 and Min Max Units
ed
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
by
3. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. 4. The propagation delay, tPTEL, should be used when Telecom bus outputs are always driven as configured by LADDOE in the Bus Configuration register. The propagation delays, tPTELOE and tZTEL, should be used when the
Co
nt e
2. Maximum and minimum output propagation delays are measured with a 100 pF load on all the outputs.
nt Te a
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
m
of P
Notes on Telecom Bus and Line Side SBI Output Timing:
ar
tm
in
er
tPTELOE
LREFCLK rising to all Telecom BUS tristateable Outputs going valid from tristate
In
co
tZTEL
LREFCLK rising to all Telecom BUS tristateable Outputs going tristate
n
Tu
tPTEL
LREFCLK rising to LAOE and LAC1J1V1 Outputs Valid
es
Se
pt
em
tPTELOE
LREFCLK rising to all Telecom BUS tristateable Outputs going valid from tristate
be
r,
tZTEL
LREFCLK rising to all Telecom BUS tristateable Outputs going tristate
20
3
04
tPTEL
LREFCLK rising to all Telecom BUS Outputs Valid
3
07
Symbol
Description
Min
:4
7 7 7
3:
20 20 14
Table 55 - Telecom Bus and Line Side SBI Output Timing - 19.44 MHz (Figure 86 and Figure 87) Max
26
0
1 1 1
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Units
ns ns ns
ns ns ns
305
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Figure 86
- Telecom BUS and Line Side SBI Output Timing
LADATA[7:0] LADP, LAPL LAV5,LAOE LAC1J1V1
Table 57 Symbol
- System Side SBI ADD BUS Timing - 19.44 MHz (Figure 88)
m
of P
nt Te a
Description
ar
LADATA[7:0] LADP, LAPL LAV5
tm
in
er
tPTELOE
In
co
n
LREFCLK
Tu
es
da
Figure 87
- Telecom BUS and Line Side SBI Tristate Output Timing
y,
14
Se
pt
tPTEL
em
tZ TEL
be
LREFCLK
Min
r,
20
04
Max
07
:4
Telecom bus outputs are multiplexed with other TEMUX 84 devices using the tristate capability of the outputs as configured by LADDOE. Note that under any specific operating condition, tZTEL is guaranteed to be less than tPTELOE.
3:
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Units
SREFCLK Frequency SREFCLK Duty Cycle All SBI ADD BUS Inputs Set-Up Time to SREFCLK All SBI ADD BUS Inputs Hold Time to SREFCLK SREFCLK to SAJUST_REQ Valid
nt e
19.44 -20 ppm 40 4 0 2
19.44 +20 ppm 60
MHz % ns ns
tSSBIADD
ad
ed
by
tHSBIADD tPSBIADD
Co
Do wn lo
15
ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
306
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Notes on System Side SBI Input Timing:
2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
in
er
In
co
n
Tu
tZSBIADD
SREFCLK to SAJUST_REQ Tristate
es
tPSBIADD
SREFCLK to SAJUST_REQ Valid
da
y,
tHSBIADD
All SBI ADD BUS Inputs Hold Time to SREFCLK
14
Se
tSSBIADD
All SBI ADD BUS Inputs Set-Up Time to SREFCLK
pt
SREFCLK Duty Cycle
em
be
SREFCLK Frequency
77.76 -20 ppm 40 2.7 0 1 1
r,
20
Symbol
Description
Min
04
Table 58
- System Side SBI ADD BUS Timing - 77.76 MHz (Figure 88) Max Units
07
:4
tZSBIADD
SREFCLK to SAJUST_REQ Tristate
2
15
3:
26
Symbol
Description
Min
Max
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Units
ns
77.76 +20 ppm 60
MHz % ns ns
6 6
ns ns
307
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tZSBIDROP tPOUTEN
nt Te a
m
tPSBIDROP
SREFCLK to All SBI DROP BUS Outputs except SDC1FP Valid
of P
tPSDC1FP
SREFCLK to SDC1FP Output Valid
ar
tHSBIDROP
SDC1FP Hold Time to SREFCLK
tm
in
tSSBIDROP
SDC1FP Set-Up Time to SREFCLK
er
In
Symbol
Description
co
Table 59 - System Side SBI DROP BUS Timing - 19.44 MHz (Figure 86 and Figure 89)
n
Tu
es
da
y,
SAJUST_REQ
14
Se
tZSBIADD
pt
tPSBIADD
em
SC1FP SADATA[7:0] SADP,SAPL SAV5
be
r,
20
tSSBIADD
tHSBIADD
Min
04
Max
07
Units
SREFCLK
4 0 2 2 2 0 0 4 0 17 17 16 17 16
:4
ns ns ns ns ns ns ns ns ns SREFCLK to All SBI DROP BUS Outputs except SDC1FP Tristate SBIDET[1] and SBIDET[0] low to All SBI DROP BUS Outputs Valid SBIDET[1] and SBIDET[0] high to All SBI DROP BUS Outputs Tristate SBIDET[n] Set-Up Time to SREFCLK SBIDET[n] Hold Time to SREFCLK
ed
ad
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
tZOUTEN tSDET tHDET
Co
nt e
3:
308
26
Figure 88
- System Side SBI ADD BUS Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
3. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current.
in
er
In
co
2. Maximum and minimum output propagation delays are measured with a 100 pF load on all the outputs.
n
Tu
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
es
da
y,
Notes on System Side SBI Output Timing:
14
Se
tZSBIDROP
SREFCLK to All SBI DROP BUS Outputs except SDC1FP Tristate
pt
em
tPSBIDROP
SREFCLK to All SBI DROP BUS Outputs except SDC1FP Valid
be
tPSDC1FP
SREFCLK to SDC1FP Output Valid
20
tHSBIDROP
SDC1FP Hold Time to SREFCLK
0
04
tSSBIDROP
SDC1FP Set-Up Time to SREFCLK
3
07
Symbol
Description
Min
:4
7 7 7
3:
Max Units
Table 60 Figure 90)
26
- System Side SBI DROP BUS Timing - 77.76 MHz (Figure 89 to
1
r,
1 1
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
ns ns ns ns ns
309
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
SDDATA[7:0] SDDP, SDPL SDV5,SBIACT
y,
nt Te a
SREFCLK
m
of P
Figure 90
- SBI System Side DROP BUS Collision Avoidance Timing
ar
tm
by
Co
SBIDET[n] tPOUTEN tZOUTEN
ed
Do wn lo
SDDATA[7:0] SDDP, SDPL SDV5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
nt e
tSDET
in
er
SDC1FP
In
tSSBID RO P
co
SDDATA[7:0] SDDP, SDPL SDV5
n
Tu
es
da
tHDET
14
Se
tZ SBIDRO P
tHSBIDRO P
pt
tP S BIDROP
em
be
SDC1FP
r,
20
tP SD C1FP
04
07
SREFCLK
:4
3:
310
26
Figure 89
- SBI System Side DROP BUS Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
EFBWCLK[n] High Phase EFBWCLK[n] Low Phase tSEFBW tHEFBW tPEFBW
Figure 91
7 7 4
20
04
EFBWCLK[n] Frequency
0
07
Symbol
Description
Min
:4
Max
3:
Units
Table 61
- Egress Flexible Bandwidth Port Timing (Figure 91)
52
26
MHz ns ns ns ns ns
Units
- Egress Flexible Bandwidth Port Timing
EFBWCLK[n]
In
tS EFBW
co
n
Tu
es
da
EFBWCLK[n] Falling Edge to EFBWDAT[n] and EFBWEN[n] Valid
14
EFBWDREQ[n] Hold Time to EFBWCLK[n] Rising Edge
pt
EFBWDREQ[n] Set-Up Time to EFBWCLK[n] Rising Edge
Se
em
be
0 2 15
y,
tH EFBW
ar
tm
EFBWDREQ[n]
in
er
Table 62
Symbol
nt e
nt Te a
m
- Ingress Flexible Bandwidth Port Timing (Figure 92) Description Min Max
Co
of P
tP EFBW
EFBWDAT[n], EFBWEN[n]
IFBWCLK[n] Frequency IFBWCLK[n] High Phase IFBWCLK[n] Low Phase IFBWDAT[n] and IFBWEN[n] Set-Up Time to IFBWCLK[n] Rising Edge
0 7 7 4
r,
52
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
MHz ns ns ns
ad Do wn lo
ed
tSIFBW
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
by
311
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tS IFBW IFBWDAT[n], IFBWEN[n]
tH IFBW
Table 63
nt e
Symbol
nt Te a
m
4. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs.
- H-MVIP Egress Timing (Figure 93) Description Min Max Units
of P
by
Co
CMV8MCLK Frequency (See Note 3)
ar
3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
tm
in
2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
er
In
co
1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
n
Tu
es
da
Notes on Flexible Bandwidth Port Timing:
y,
14
Se
pt
em
be
IFBWCLK[n]
r,
20
16.384 -50 pp m 40 4.092 40
04
Figure 92
- Ingress Flexible Bandwidth Port Timing
07
:4
tHIFBW
IFBWDAT[n] and IFBWEN[n] Hold Time to IFBWCLK[n] Rising Edge
1
3:
16.384 +50 pp m 60 4.100 60
26
Symbol
Description
Min
Max
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Units
ns
MHz
ed
CMV8MCLK Duty Cycle CMVFPC Frequency (See Note 4) CMVFPC Duty Cycle
% MHz %
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
312
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
tSHMVED tHHMVED tSMVFPB tHMVFPB
CMVFPB Hold Time
em
be
CMVFPB Set-Up Time
r,
MVED[21:1], CASED[21:1], CCSED[3:1] Hold Time
20
5
04
MVED[21:1], CASED[21:1], CCSED[3:1] Set-Up Time
5
07
:4
tPMVC
CMV8MCLK to CMVFPC skew
-10
3:
10
26
Symbol
Description
Min
Max
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Units
ns ns ns ns ns
5
5
Notes on H-MVIP Egress Timing:
3. Measured between any two CMV8MCLK falling edges.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
4. Measured between any two CMVFPC falling edges.
er
In
co
2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
n
Tu
es
1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
da
y,
14
Se
pt
313
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
CMVFPB
CMV8MCLK
Notes on H-MVIP Ingress Timing:
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
3. Output propagation delays of signal outputs that are specified in relation to a reference output are measured with a 50 pF load on both the signal output and the reference output.
by
Co
nt e
2. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs.
nt Te a
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
m
of P
ar
tPHMVID
CMV8MCLK Low to MVID[21:1], CASID[21:1], CCSID[3:1], TS0ID Valid
tm
in
Symbol
Description
er
In
Table 64
- H-MVIP Ingress Timing (Figure 94) Min Max Units
co
n
Tu
MVED[x] CASED[x] CCSED[x]
es
da
tSHMVED
y,
14
Se
pt
tPMVC
em
be
r,
4
20
tSMVFPB
tHMVFPB
04
tHHMVED 25
07
ns
CMVFPC
:4
3:
314
26
Figure 93
- H-MVIP Egress Data & Frame Pulse Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
ar
tm
Figure 95
- XCLK Input Timing
in
er
In
co
tXCLK
XCLK_T1 and E1_XLK Period (typically 1/37.056 MHz 32 ppm for XCLK_T1 and 1/49.152 MHz for XCLK_E1)
Tu
tHXCLK
XCLK_T1 and XCLK_E1 High Pulse Width
es
da
tLXCLK
XCLK_T1 and XCLK_E1 Low Pulse Width
14
Symbol
Description
Se
Table 65
- XCLK Input (Figure 95)
pt
em
MVID[x] CASID[x] CCSID[x]
be
r,
20
tPHMVID
Min
04
Max
07
Units
CMV8MCLK
y,
8 8 20
:4
ns ns ns
n
nt Te a
XCLK_T1 or XCLK_E1
m
of P
t HXCLK t XCLK
t L XCLK
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
3:
315
26
Figure 94
- H-MVIP Ingress Data Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
es
da
CTCLK
y,
Notes on Ingress and Egress Serial Interface Timing:
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
4. Setup, hold, and propagation delay specifications are shown relative to the default active clock edge, but are equally valid when the opposite edge is selected as the active edge. 5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
Co
nt e
3. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
nt Te a
m
2. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
of P
ar
tm
1. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is measured from the 1.4 Volt points of the fall and rise ramps.
in
er
In
co
n
Tu
t L CTCLK
14
t HCTCLK
Se
t CTCLK
pt
Figure 96
- Transmit Line Interface Timing
em
be
tLCTCLK
CTCLK Low Duration
r,
tHCTCLK
CTCLK High Duration
20
60 60
04
CTCLK Frequency (Must be integer multiple of 8 KHz.)
0.008
07
Symbol
Description
Min
:4
3:
Max Units
Table 66
- Transmit Line Interface Timing (Figure 96)
2.048
26
MHz ns ns
316
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Symbol
Description
20
Min
04
Max
Table 67
- Remote Serial Alarm Port Timing
07
6. Output propagation delays are measured with a 50 pF load on all outputs with the exception of the high speed DS3/E3 outputs (TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1]). The TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1] output propagation delays are measured with a 20 pF load.
:4
3:
10 60
26
ar
RADEASTCK/ RADWESTCK RADEASTFP/ RADWESTFP
tm
in
er
In
Figure 97
- Remote Serial Alarm Port Timing
co
m
of P
tSRADFP
n
tSRAD
RADEAST and RADWEST Setup Time
Tu
tHRAD
RADEAST and RADWEST Hold Time
es
da
tSRADFP
RADEASTFP and RADWESTFP Setup Time
y,
14
tHRADFP
RADEASTFP and RADWESTFP Hold Time
Se
RADEASTCK and RADWESTCK Duty Cycle
em
RADEASTCK and RADWESTCK Frequency
r,
be
1.344 40 5 5 5 5
pt
tHRADFP
tSRAD
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
tHRAD
RADEAST/ RADWEST
AM
%
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Units
MHz
ns ns ns ns
317
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
in
er
In
co
n
Tu
es
tVTRSTB
da
TRSTB Pulse Width
y,
tPTDO
TCK Low to TDO Valid
14
tHTDI
TDI Hold time to TCK
Se
pt
tSTDI
TDI Set-up time to TCK
em
tHTMS
TMS Hold time to TCK
be
tSTMS
50
r,
TMS Set-up time to TCK
50
20
TCK Duty Cycle
40
04
TCK Frequency
07
1
Symbol
Description
Min
Max
:4
3:
Units
Table 68
- JTAG Port Interface
26
MHz % ns ns ns ns 50 ns ns 60 50 50 2 100
318
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
TMS tS TDI TDI tH TDI
TCK
TDO
In
co
n
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
nt e
nt Te a
m
of P
ar
tm
TRSTB
in
er
Tu
es
tP TDO
tV TRSTB
da
y,
14
Se
pt
em
be
r,
20
04
tS TMS
tH TMS
07
TCK
:4
3:
319
26
Figure 98
- JTAG Port Interface Timing
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
PM8316-PI
324 Plastic Ball Grid Array (PBGA)
pt
em
This product is designed to operate over a wide temperature range and is suited for industrial applications such as central office equipment or in-field locations.
be
r,
20
04
105 0C 125 0C -40 0C 400 LFM 12.4
Part No.
Description
Minimum ambient temperature Thermal Resistance vs Air Flow Airflow
JA ( C/W)
0
18.6
3
co
n
Natural Convection
Tu
2
es
da
y,
Maximum junction temperature for short-term excursions with guaranteed 1 continued functional performance. This condition will typically be reached when local ambient reaches 70 Deg C.
in
JT (0C/W) JB (0C/W)
er
Device Compact Model
In
14
Se
Maximum long-term operating junction temperature to ensure adequate long-term life
200 LFM 15.2
5.6 11.5
Ambient JT Junction JB Board
Device Compact Model
Power (watts)
of P
Operating power is dissipated in package (watts) at worst case power supply 1.0W
Notes
1. 2. 3.
Short-term is understood as the definition stated in Bellcore Generic Requirements GR-63-Core.
Do wn lo
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
ad
ed
by
Co
JB, the junction-to-board thermal resistance and JT, the residual junction to ambient thermal resistance are obtained by simulating conditions described in JEDEC Standard, JESD 15-8.
nt e
JA , the total junction to ambient thermal resistance as measured according to JEDEC Standard JESD51 (2S2P)
nt Te a
m
ar
tm
07
Table 69
- Ordering Information
:4
3:
320
18
ORDERING AND THERMAL INFORMATION
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
0.20
(4X )
04
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22 21 20 18 17 16
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- 324 Pin PBGA 23x23mm Body
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0.30 M C A B 0.10 M C B
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MECHANICAL INFORMATION
D1
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19.00 19.50 20.20
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0.55 0.61 0.67 23.00
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0.50 0.63 0.70 1.00 1.00 0.15 0.35
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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26
A1 BAL L CORNER
2 1 A B C D E F G H J K L M N P R T U V W Y AA AB
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
321
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA AND FOR ITS CUSTOMERS' INTERNAL USE
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26
NOTES
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RELEASED DATA SHEET PMC-1991437 ISSUE 8
PM8316 TEMUX 84
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7
Document Information: Corporate Information: Application Information: Web Site:
document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
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(c) 2003 PMC-Sierra, Inc. Issue date: January 2003
PMC-1991437 (R8) ref PMC-991191 (R9)
PMC-Sierra, Inc.
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In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.
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None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.
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8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
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Fax:
(604) 415-6200
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Tel:
(604) 415-6000
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CONTACTING PMC-SIERRA, INC.
26
AM
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX

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